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db_rfic.cc @ 501

Revision 501, 131.2 KB (checked in by sriram, 15 years ago)
Working driver code

Line
1	#ifndef DB_RFIC_H
2	#define DB_RFIC_H
3	#include <db_rfic.h>
4	#include <db_base_impl.h>
5	#include <cmath>
6	#include <boost/thread.hpp>
7	#include <boost/weak_ptr.hpp>
8
9	int TX_EN = (1<<6);
10
11	struct rfic_key {
12	std::string serial_no;
13	int which;
14
15	bool operator==(const rfic_key &x){
16	return x.serial_no ==serial_no && x.which == which;
17	}
18	};
19
20	class rfic{
21
22	public:
23	usrp_basic *d_raw_usrp;
24	int d_which;
25	bool d_is_shutdown;
26	int d_spi_format, d_spi_enable,d_spi_format_no_header;
27	int Ngt3, NorNdiv4, RorFrNpRdiv4_25to18, RorFrNpRdiv4_17to10, RorFrNpRdiv4_9to2, RorFrNpRdiv4_1to0, Qu_tx_Ngt3 \
28	,NorNdiv4_phsh, RorFrNpRdiv4_phsh_25to18, RorFrNpRdiv4_phsh_17to10, RorFrNpRdiv4_phsh_9to2, \
29	RorFrNpRdiv4_phsh_1to0, Passthru_ref_clk, Byp_ram, Dis_adr_dith, Dis_p5G_dith, Byp_fine, Exclude32, Dis_risedge \
30	, Dis_faledge, Spr_puls_en, Spr_puls_val_a_9to3, Spr_pulse_val_2to0, Spr_puls_val_b_9to2, Spr_puls_val_b_1to0 \
31	,Thru_ris_en, Thru_ris_tap_11to6, Thru_ris_tap_5to0, Thru_fal_en, Thru_fal_tap_11to6, Thru_fal_tap_5to0, \
32	Dig_delay, Clk_driver_en, qu_reg_en, qq_reg_en, win_rst, fineEn, fineEnb, rsffEn, dl_en, cp_en, forceCpUpb, \
33	forceCpDn, pdUpTune_1to0, pdDnTune_1to0, cpUpTune_2to0, cpDnTune_2to0, pdEn, digClkPhase_7to0, Rst_n_async;
34
35	std::string L1_lup00_15to8; //Read-only//
36	std::string L1_lup90_15to8; //Read-only//
37	std::string Merg_ris_fin; //Read-only//
38	std::string Merg_fal_fin; //Read-only//
39
40	int Qg00degDelay_0to4 ,Qg90degDelay_0to4, Qg180degDelay_0to4, Qg270degDelay_0to4, DischargeTap16_0to3, \
41	ChargeTap16_0to3, DischargeTapn_0to3, ChargeTapn16_0to3, X1sel_32to39, X1sel_40to47,X2sel_32to36, X2sel_37to41 \
42	,X4sel_32to36, X4sel_37to41, X8sel_32to36, X8sel_41, X8sel_37to40, qutx_fwd_180Cal_en, qutx_fwd_0Cal_en;
43	//-------------------------------------------------------------------------------------------------------
44	// TRANSMIT FEEDBACK QuIET FREQUENCY GENERATOR
45	//-------------------------------------------------------------------------------------------------------
46	int Ngt3_2, NorNdiv4_2, RorFrNpRdiv4_25to18_2, RorFrNpRdiv4_17to10_2, RorFrNpRdiv4_9to2_2, RorFrNpRdiv4_1to0_2, \
47	Qu_tx_Ngt3_2, NorNdiv4_phsh_2, RorFrNpRdiv4_phsh_25to18_2, RorFrNpRdiv4_phsh_17to10_2, RorFrNpRdiv4_phsh_9to2_2, \
48	RorFrNpRdiv4_phsh_1to0_2, Passthru_ref_clk_2, Byp_ram_2, Dis_adr_dith_2, Dis_p5G_dith_2, Byp_fine_2, \
49	Exclude32_2, Dis_risedge_2, Dis_faledge_2, Spr_puls_en_2, Spr_puls_val_a_9to3_2, Spr_pulse_val_2to0_2, \
50	Spr_puls_val_b_9to2_2, Spr_puls_val_b_1to0_2, Thru_ris_en_2, Thru_ris_tap_11to6_2, Thru_ris_tap_5to0_2, \
51	Thru_fal_en_2, Thru_fal_tap_11to6_2, Thru_fal_tap_5to0_2, Dig_delay_2, Clk_driver_en_2, qu_reg_en_2, \
52	qq_reg_en_2, win_rst_2 , fineEn_2, fineEnb_2, rsffEn_2, dl_en_2, cp_en_2, forceCpUpb_2, forceCpDn_2, \
53	pdUpTune_1to0_2, pdDnTune_1to0_2, cpUpTune_2to0_2, cpDnTune_2to0_2, pdEn_2 , digClkPhase_7to0_2, Rst_n_async_2;
54
55	std::string L1_lup00_15to8_2; //Read-only//
56	std::string L1_lup90_15to8_2; //Read-only//
57	std::string Merg_ris_fin_2; //Read-only//
58	std::string Merg_fal_fin_2; //Read-only//
59	std::string Decod_in_0deg;
60	std::string L1_lup00_15to8_3;
61	std::string L1_lup90_15to8_3;
62	std::string Merg_ris_fin_3;
63	std::string Merg_fal_fin_3;
64
65
66	int Qg00degDelay_0to4_2, Qg90degDelay_0to4_2, Qg180degDelay_0to4_2, Qg270degDelay_0to4_2, DischargeTap16_3to0;
67
68
69	int ChargeTap16_3to0, DischargeTapn_3to0 , ChargeTapn16_3to0, X1sel_32to39_2;
70	int X1sel_40to47_2, X2sel_32to36_2, X2sel_37to41_2, X4sel_32to36_2, X4sel_37to41_2, X8sel_32to36_2, X8sel_41_2;
71	int X8sel_37to40_2, qutx_fb_180Cal_en, qutx_fb_0Cal_en, qutx_fb_180Rsff_en, qutx_fb_0Rsff_en, N, R_11to8;
72	int R_7to0, Asyncrst_n, Cp_sel_6to0, Cp_sel_8to7, ForceFout, ForceFoutb, Out_en, Dll_en, Ana_en, Ngt3_3;
73	int NorNdiv4_3, RorFrNpRdiv4_25to18_3, RorFrNpRdiv4_17to10_3, RorFrNpRdiv4_9to2_3, RorFrNpRdiv4_1to0_3;
74	int Qu_tx_Ngt3_3, NorNdiv4_phsh_3, RorFrNpRdiv4_phsh_25to18_3, RorFrNpRdiv4_phsh_17to10_3, RorFrNpRdiv4_phsh_9to2_3;
75	int RorFrNpRdiv4_phsh_1to0_3, Passthru_ref_clk_3, Byp_ram_3, Dis_adr_dith_3, Dis_p5G_dith_3, Byp_fine_3;
76	int Exclude32_3, Dis_risedge_3, Dis_faledge_3, Spr_puls_en_3, Spr_puls_val_a_9to3_3, Spr_pulse_val_2to0_3;
77	int Spr_puls_val_b_9to2_3, Spr_puls_val_b_1to0_3, Thru_ris_en_3, Thru_ris_tap_11to6_3, Thru_ris_tap_5to0_3;
78	int Thru_fal_en_3, Thru_fal_tap_11to6_3, Thru_fal_tap_5to0_3, Dig_delay_3, Clk_driver_en_3, qu_reg_en_3;
79	int qq_reg_en_3, win_rst_3, fineEn_3, fineEnb_3, rsffEn_3, dl_en_3, cp_en_3, forceCpUpb_3, forceCpDn_3;
80	int pdUpTune_1to0_3, pdDnTune_1to0_3, cpUpTune_2to0_3, cpDnTune_2to0_3, pdEn_3, digClkPhase_7to0_3, Rst_n_async_3;
81	int Qg00degDelay_0to4_3, Qg90degDelay_0to4_3, Qg180degDelay_0to4_3, Qg270degDelay_0to4_3, DischargeTap16_0to3_3;
82	int ChargeTap16_0to3_3, DischargeTapn_0to3_3, ChargeTapn16_0to3_3, X1sel_32to39_3, X1sel_40to47_3, X2sel_32to36_3;
83	int X2sel_37to41_3, X4sel_32to36_3, X4sel_37to41_3, X8sel_32to36_3, X8sel_41_3, X8sel_37to40_3, qurx_180Cal_en;
84	int qurx_0Cal_en, extClkEn, extClkEnBNOTD7, div2_rst, TxChClkSel, TxChClkEn, tx_bb_en, tx_bb_fdbk_bw;
85	int tx_bb_fdbk_cal_en, tx_bb_fdbk_cart_err_en, tx_bb_fdbk_cart_fb_en, tx_bb_fdbk_cart_fwd_en, tx_bb_fdbk_en;
86	int tx_bb_fdbk_1q_sel, tx_bb_fdbk_lp, tx_bb_fdbk_statt, tx_bb_fdbk_swapi, tx_bb_fdbk_swapq, tx_bb_gain_cmp;
87	int tx_bb_lp, tx_bb_swapi, tx_bb_swapq, tx_butt_bw, tx_bw_trck, tx_cart_en, tx_cart_fb_bb_statt;
88	int tx_cart_fb_dcoc_dac_I1, tx_cart_fb_dcoc_dac_I2, tx_cart_fb_dcoc_dac_Q1, tx_cart_fb_dcoc_dac_Q2;
89	int CartesianFeedbackpathDCOCenable, CartesianFeedbackpathenable, CartesianFBpathHiResolutionDCOCenable;
90	int CartesianFBpathBW, CartesianFBRFGain, CartesianFBpathSwapIandIx, CartesianFBpathSwapQandQx;
91	int CartesianFBpathSwitchtoforwardSummer, tx_cart_fb_lo_select, CartesianFBpathAmp1Gain, CartesianFBpathAmp2Gain;
92	int CartesianFBpathAmp3Gain, CartesianFBpathAmp4Gain, CartesianFBpathAmpCurrentSelect, CartesianFBpathZeroEnable;
93	int tx_cart_zero_statt, tx_inbuf_bw, tx_inbuf_statt, tx_output_channel_sel, tx_p1_bw, tx_pw_bw1, tx_p2_bw2; int PushPullBufferCurrent, tx_rf_aoc_bw, RFForwardPathEnable_toMUX, RFForwardPathEnable_ExternalPinenable;
94	int tx_rf_fwd_lp, tx_rf_fwd_statt1, tx_rf_fwd_statt2, BBQDivideby2or4Select, BBQQuadGenEnable;
95	int BBQPolyphaseQuadGenEnable, lofb_tun_s, lofb_tun_sx, lofw_tun_s2, lofw_tun_sx2, reserve_tx26, reserve_tx27;
96	int rx_Idac, rx_dcs, rx_den, rx_Qdac, rx_cmpen, rx_dcoc, rx_ten, rx_ren, rx_dven, rx_dv, rx_extc, rx_cen;
97	int rx_chck, rx_chcken, rx_fen, rx_onchen, rx_offchen, rx_foe, rx_offch, rx_onchf, rx_onchc, rx_qs, rx_bqg;
98	int rx_rq, rx_rv, rx_rip, rx_rfp, rx_cp_12to8, rx_gs, rx_cp_7to0, rx_cv_10to3, rx_cv_2to0, rx_cc_2to0;
99	int rx_cq_9to8, rx_cq_7to0, rx_lna, rx_lnab, rx_rxchen, rx_bbq_div2or4, rx_Loselect, poly_en, lorx_tun_s, lorx_tun_sx;
100
101	std::string rx_Icmpo; //I path DCOC comparator output. Output of the DCOC comparator - used for test purposes. Output only.//
102	std::string rx_Iodac; //I path DCOC DAC output. Output of the DCOC DACs - used to read result of DCOC correction circuitry. Output only.//
103	std::string rx_Qcmpo; //Q path DCOC comparator output. Output of the DCOC comparator - used for test purposes. Output only.//
104	std::string rx_Qodac; //Q path DCOC DAC output. Output of the DCOC DACs - used to read result of DCOC correction circuitry. Output only.//
105	std::string rx_rc;
106
107	int shft_cml_in, vagenable1, vagenable2, TestMuxBufferEnable, TestMuxEnable, TestMuxSetting, txgain;
108
109	float Foutrx,Fclk,Fouttx, Foutrxb, Foutfb;
110
111	int Rst_n_async2,Rst_n_async3; //generated inside function in python code..have to be declared in c++
112	// Initialize GPIO and ATR
113	// GPIO are the general-purpose IO pins on the daughterboard
114	// IO_RX_06 must be used for ATR (1 = TX, 0 = RX)
115	// ATR is the automatic transmit/receive switching, done in the FPGA
116	// FIXME
117
118
119
120
121	usrp_basic *usrp(){
122	return d_raw_usrp;
123	}
124
125	rfic(usrp_basic_sptr usrp, int which);
126	~rfic();
127
128	bool rx_write_io(int, int); //the defination may need to be changed..mask should be a hex value...will rework this
129	bool rx_write_oe(int,int);
130	bool rx_set_atr_rxval(int);
131	bool rx_set_atr_txval(int);
132	bool rx_set_atr_mask(int);
133
134
135	void shutdown();
136	void send_reg(int,int);
137
138	//send register wrapper function difinations//
139	void set_reg_0();
140	void set_reg_1();
141	void set_reg_2();
142	void set_reg_3();
143	void set_reg_4();
144	void set_reg_5();
145	void set_reg_6();
146	void set_reg_7();
147	void set_reg_8();
148	void set_reg_9();
149	void set_reg_10();
150	void set_reg_12();
151	void set_reg_13();
152	void set_reg_14();
153	void set_reg_15();
154	void set_reg_16();
155	void set_reg_17();
156	void set_reg_18();
157	void set_reg_19();
158	void set_reg_20();
159	void set_reg_21();
160	void set_reg_22();
161	void set_reg_23();
162	void set_reg_24();
163	void set_reg_29();
164	void set_reg_30();
165	void set_reg_31();
166	void set_reg_32();
167	void set_reg_33();
168	void set_reg_34();
169	void set_reg_35();
170	void set_reg_36();
171	void set_reg_37();
172	void set_reg_38();
173	void set_reg_39();
174	void set_reg_40();
175	void set_reg_41();
176	void set_reg_42();
177	void set_reg_43();
178	void set_reg_48();
179	void set_reg_49();
180	void set_reg_50();
181	void set_reg_51();
182	void set_reg_52();
183	void set_reg_53();
184	void set_reg_54();
185	void set_reg_55();
186	void set_reg_56();
187	void set_reg_57();
188	void set_reg_58();
189	void set_reg_60();
190	void set_reg_61();
191	void set_reg_62();
192	void set_reg_63();
193	void set_reg_64();
194	void set_reg_65();
195	void set_reg_66();
196	void set_reg_67();
197	void set_reg_68();
198	void set_reg_69();
199	void set_reg_70();
200	void set_reg_71();
201	void set_reg_72();
202	void set_reg_77();
203	void set_reg_78();
204	void set_reg_79();
205	void set_reg_80();
206	void set_reg_81();
207	void set_reg_82();
208	void set_reg_83();
209	void set_reg_84();
210	void set_reg_85();
211	void set_reg_86();
212	void set_reg_87();
213	void set_reg_88();
214	void set_reg_89();
215	void set_reg_90();
216	void set_reg_91();
217	void set_reg_96();
218	void set_reg_97();
219	void set_reg_98();
220	void set_reg_99();
221	void set_reg_104();
222	void set_reg_105();
223	void set_reg_106();
224	void set_reg_107();
225	void set_reg_108();
226	void set_reg_109();
227	void set_reg_110();
228	void set_reg_111();
229	void set_reg_112();
230	void set_reg_113();
231	void set_reg_114();
232	void set_reg_116();
233	void set_reg_117();
234	void set_reg_118();
235	void set_reg_119();
236	void set_reg_120();
237	void set_reg_121();
238	void set_reg_122();
239	void set_reg_123();
240	void set_reg_124();
241	void set_reg_125();
242	void set_reg_126();
243	void set_reg_127();
244	void set_reg_128();
245	void set_reg_133();
246	void set_reg_134();
247	void set_reg_135();
248	void set_reg_136();
249	void set_reg_137();
250	void set_reg_138();
251	void set_reg_139();
252	void set_reg_140();
253	void set_reg_141();
254	void set_reg_142();
255	void set_reg_143();
256	void set_reg_144();
257	void set_reg_145();
258	void set_reg_146();
259	void set_reg_147();
260	void set_reg_152();
261	void set_reg_153();
262	void set_reg_156();
263	void set_reg_157();
264	void set_reg_158();
265	void set_reg_159();
266	void set_reg_160();
267	void set_reg_161();
268	void set_reg_162();
269	void set_reg_163();
270	void set_reg_164();
271	void set_reg_165();
272	void set_reg_166();
273	void set_reg_167();
274	void set_reg_168();
275	void set_reg_169();
276	void set_reg_170();
277	void set_reg_171();
278	void set_reg_172();
279	void set_reg_173();
280	void set_reg_174();
281	void set_reg_175();
282	void set_reg_176();
283	void set_reg_177();
284	void set_reg_178();
285	void set_reg_179();
286	void set_reg_180();
287	void set_reg_181();
288	void set_reg_192();
289	void set_reg_193();
290	void set_reg_194();
291	void set_reg_195();
292	void set_reg_196();
293	void set_reg_197();
294	void set_reg_198();
295	void set_reg_199();
296	void set_reg_200();
297	void set_reg_201();
298	void set_reg_202();
299	void set_reg_203();
300	void set_reg_204();
301	void set_reg_205();
302	void set_reg_206();
303	void set_reg_207();
304	void set_reg_220();
305	void set_reg_222();
306	//
307
308	void read_reg_25();
309	void read_reg_26();
310	void read_reg_27();
311	void read_reg_28();
312	void read_reg_73();
313	void read_reg_74();
314	void read_reg_75();
315	void read_reg_76();
316	void read_reg_100();
317	void read_reg_125();
318	void read_reg_129();
319	void read_reg_130();
320	void read_reg_131();
321	void read_reg_132();
322	void read_reg_208();
323	void read_reg_209();
324	void read_reg_210();
325
326	char get_reg(int);
327	bool set_rx_gain(float);
328	bool set_tx_gain(float);
329	void set_fb_gain(float);
330	void calc_freq_vars(double,double,int []);
331	void calc_phase_vars(double,double,double,int[]);
332	struct freq_result_t set_rx_freq(double);
333	struct freq_result_t set_tx_freq(double);
334	bool set_fb_freq(double);
335
336	bool set_rx_phase(int);
337	bool set_tx_phase(int);
338
339	bool set_fb_phase(int);
340	bool set_rx_bw(float);
341	bool set_tx_bw(float);
342	void set_fb_bw(float);
343	void enable_tx_fb();
344	void disable_tx_fb();
345	int RSSI_fade();
346	int RSSI_clip();
347
348	};
349
350
351	/***************************method definitions***************************/
352
353	rfic::rfic(usrp_basic_sptr _usrp, int which)
354	: d_raw_usrp(_usrp.get()), d_which(which)
355	{
356	Ngt3 = 0; //Output frequency control bit. Calculated.//
357	NorNdiv4 = 1; //Output frequency control word. Calculated.//
358	RorFrNpRdiv4_25to18 = 0; //Output frequency control word. Calculated//
359	RorFrNpRdiv4_17to10 = 0; ////
360	RorFrNpRdiv4_9to2 = 0; ////
361	RorFrNpRdiv4_1to0 = 0; ////
362	Qu_tx_Ngt3 = 0; //Enables divide-by-4 freq divider - Phase shift control bit. Calculated//
363	NorNdiv4_phsh = 1; //Phase shift control word. Calculated.//
364	RorFrNpRdiv4_phsh_25to18 = 0; //Phase shift control word. Calculated.//
365	RorFrNpRdiv4_phsh_17to10 = 0; ////
366	RorFrNpRdiv4_phsh_9to2 = 0; ////
367	RorFrNpRdiv4_phsh_1to0 = 0; ////
368	Passthru_ref_clk = 0; //A test mode where the 1 GHz input reference is passed directly to the output//
369	Byp_ram = 1; //Bypass the SRAMs//
370	Dis_adr_dith = 1; //Disable the dither generator in the ca2adr block//
371	Dis_p5G_dith = 1; //Disable the dither generator in the lup2decod block//
372	Byp_fine = 1; //Bypass fine delay line control bit//
373	Exclude32 = 0; //Bypass fine delay line control bit (exclude 32)//
374	Dis_risedge = 0; //Disable the rising edges decoders//
375	Dis_faledge = 0; //Disable the falling edges decoders//
376	Spr_puls_en = 0; //enable spur pulsing//
377	Spr_puls_val_a_9to3 = 0; //spur pulsing control word//
378	Spr_pulse_val_2to0 = 0; ////
379	Spr_puls_val_b_9to2 = 8; //spur pulsing control word//
380	Spr_puls_val_b_1to0 = 0 ;////
381	Thru_ris_en = 0; //Put rising edges decoders into through-tap mode//
382	Thru_ris_tap_11to6 = 32; //Through-tap control word//
383	Thru_ris_tap_5to0 = 0; ////
384	Thru_fal_en = 0; //Put falling edges decoders into through-tap mode//
385	Thru_fal_tap_11to6 = 32; //Through-tap control word//
386	Thru_fal_tap_5to0 = 0; ////
387	Dig_delay = 0; //This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control.//
388	Clk_driver_en = 0; //This allows the clock to reach the digital block. It first passes through the digital/analog clock synchronization mux, which means that dlEn must be on (dlEn=1) and Clk_driver=1 for the digital block to receive a clock. See Byp_fine, address 10, bit 6//
389	qu_reg_en = 0; //This bit enables the voltage regulators that supply 1.2 V to all the analog block functions. There are 6 separate regulators that are simultaneously enabled by this bit.//
390	qq_reg_en = 0; //This bit enables the voltage regulators that supply 1.2 V to all the Quad Gen functions. There are 3 separate regulators that are simultaneously enabled by this bit.//
391	win_rst = 0; //When this bit is high, the windowing function is in a reset state, which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block.//
392	fineEn = 0; //This bit, when high, routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS. When low, the coarse tap is routed directly to the output RS Flip Flop.//
393	fineEnb = 0; //Opposite of fineEn//
394	rsffEn = 0; //This bit must be high to send the QuIET 0 and 180 degree calibration signals off chip. It does not control the RS Flip Flop outputs of the DDS, though it may have some second order (coupling) effect.//
395	dl_en = 1; //Allows the PLL reference to enter the QuIET delay line when enabled.//
396	cp_en = 1; //This bit, when enables, activates the charge pump that controls the delay line via the single pole (one capacitor) DLL loop filter.//
397	forceCpUpb = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the pmos device connected to the DLL loop filter cap turns on and sources current into the cap, thereby increasing the delay line control voltage. //
398	forceCpDn = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the nmos device connected to the DLL loop filter cap turns off and allows the pmos device to charge up the loop cap as described above.//
399	pdUpTune_1to0 = 3; //These bits control the pulse width from the phase detector into the charge up port of the charge pump. 00 turns the charge up signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
400	pdDnTune_1to0 = 0; //These bits control the pulse width from the phase detector into the charge down port of the charge pump. 00 turns the charge down signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
401	cpUpTune_2to0 = 7; //These bits control amount of current that is sourced while the charge up signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
402	cpDnTune_2to0 = 2; //These bits control amount of current that is sinked while the charge down signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
403	pdEn = 1; //When enables, the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21. When disabled, the forceCpUp and forceCpDn settings will control the charge pump.//
404	digClkPhase_7to0 = 4; //Only one bit in this field should be active at one time. This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block. This is needed to control the windowing function of the DDS.//
405	Rst_n_async = 0; //Digital reset//
406
407	Qg00degDelay_0to4 = 31; //Adjusts series delay in the 0 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
408	Qg90degDelay_0to4 = 7; //Adjusts series delay in the 90 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
409	Qg180degDelay_0to4 = 31; //Adjusts series delay in the 180 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
410	Qg270degDelay_0to4 = 7; //Adjusts series delay in the 270 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
411	DischargeTap16_0to3 = 15; //Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
412	ChargeTap16_0to3 = 4; //Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
413	DischargeTapn_0to3 = 15; //Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
414	ChargeTapn16_0to3 = 2; //Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
415	X1sel_32to39 = 0; //Control for the divide-by-two and x1 functions.//
416	X1sel_40to47 = 0; //Control for the divide-by-two and x1 functions.//
417	X2sel_32to36 = 0; //Control for the x2 function.//
418	X2sel_37to41 = 0; //Control for the x2 function.//
419	X4sel_32to36 = 0; //Control for the x4 function.//
420	X4sel_37to41 = 0; //Control for the x4 function.//
421	X8sel_32to36 = 0; //Bit 41 is used for a fine line windowing control bit. If the fine line is needed, this bit needs to be set high if Fout is close to Fref (greater than ~ 950 MHz) or for some testing modes like pass through or thru_rise_en.//
422	X8sel_41 = 0; //hiFout - set for passthrough and Fout close to Fref//
423	X8sel_37to40 = 0; ////
424	qutx_fwd_180Cal_en = 0; //Enables the pad driver that sends the falling edge signal off chip. This falling edge signal is used internally to trigger the 'Reset' pin of the output RS Flip Flop.//
425	qutx_fwd_0Cal_en = 0; //Enables the pad driver that sends the rising edge signal off chip. This rising edge signal is used internally to trigger the 'Set' pin of the output RS Flip Flop.//
426	//-------------------------------------------------------------------------------------------------------
427	// TRANSMIT FEEDBACK QuIET FREQUENCY GENERATOR
428	//-------------------------------------------------------------------------------------------------------
429	Ngt3_2 = 0; //Output frequency control bit. Calculated.//
430	NorNdiv4_2 = 1; //Output frequency control word. Calculated.//
431	RorFrNpRdiv4_25to18_2 = 0; //Output frequency control word. Calculated.//
432	RorFrNpRdiv4_17to10_2 = 0; ////
433	RorFrNpRdiv4_9to2_2 = 0; ////
434	RorFrNpRdiv4_1to0_2 = 0; ////
435	Qu_tx_Ngt3_2 = 0; //Enables divide-by-4 freq divider - Phase shift control bit. Calculated//
436	NorNdiv4_phsh_2 = 1; //Phase shift control word. Calculated//
437	RorFrNpRdiv4_phsh_25to18_2 = 0; //Phase shift control word. Calculated//
438	RorFrNpRdiv4_phsh_17to10_2 = 0; ////
439	RorFrNpRdiv4_phsh_9to2_2 = 0; ////
440	RorFrNpRdiv4_phsh_1to0_2 = 0 ;////
441	Passthru_ref_clk_2 = 0; //Enable reference clock pass-through mode//
442	Byp_ram_2 = 1; //Bypass the SRAMs//
443	Dis_adr_dith_2 = 1; //Disable the dither generator in the ca2adr block//
444	Dis_p5G_dith_2 = 1; //Disable the dither generator in the lup2decod block//
445	Byp_fine_2 = 1; //Bypass fine delay line control bit//
446	Exclude32_2 = 0; //Bypass fine delay line control bit (exclude 32)//
447	Dis_risedge_2 = 0; //Disable the rising edges decoders//
448	Dis_faledge_2 = 0;//Disable the falling edges decoders//
449	Spr_puls_en_2 = 0; //Enable spur pulsing mode//
450	Spr_puls_val_a_9to3_2 = 0; //Spur pulsing mode control word//
451	Spr_pulse_val_2to0_2 = 0; ////
452	Spr_puls_val_b_9to2_2 = 8; //Spur pulsing mode control word//
453	Spr_puls_val_b_1to0_2 = 0 ;////
454	Thru_ris_en_2 = 0; //Put rising edges decoders into through-tap mode//
455	Thru_ris_tap_11to6_2 = 32; //Through-tap mode control word//
456	Thru_ris_tap_5to0_2 = 0; //Through-tap mode control word//
457	Thru_fal_en_2 = 0; //Put falling edges decoders into through-tap mode//
458	Thru_fal_tap_11to6_2 = 32; //Through-tap mode control word//
459	Thru_fal_tap_5to0_2 = 0; //Through-tap mode control word//
460	Dig_delay_2 = 0; //This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control.//
461	Clk_driver_en_2 = 0; //This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control. See Byp_fine, address 10, bit 6//
462	qu_reg_en_2 = 0; //This bit enables the voltage regulators that supply 1.2 V to all the analog block functions. There are 6 separate regulators that are simultaneously enabled by this bit.//
463	qq_reg_en_2 = 0; //This bit enables the voltage regulators that supply 1.2 V to all the Quad Gen functions. There are 3 separate regulators that are simultaneously enabled by this bit.//
464	win_rst_2 = 0; //When this bit is high, the windowing function is in a reset state, which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block.//
465	fineEn_2 = 0; //This bit, when high, routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS. When low, the coarse tap is routed directly to the output RS Flip Flop.//
466	fineEnb_2 = 0; //Opposite of fineEn.//
467	rsffEn_2 = 0; //This bit must be high to send the QuIET 0 and 180 degree calibration signals off chip. It does not control the RS Flip Flop outputs of the DDS, though it may have some second order (coupling) effect.//
468	dl_en_2 = 1; //Allows the PLL reference to enter the QuIET delay line when enabled.//
469	cp_en_2 = 1; //This bit, when enables, activates the charge pump that controls the delay line via the single pole (one capacitor) DLL loop filter.//
470	forceCpUpb_2 = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the pmos device connected to the DLL loop filter cap turns on and sources current into the cap, thereby increasing the delay line control voltage. //
471	forceCpDn_2 = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the nmos device connected to the DLL loop filter cap turns off and allows the pmos device to charge up the loop cap as described above.//
472	pdUpTune_1to0_2 = 3; //These bits control the pulse width from the phase detector into the charge up port of the charge pump. 00 turns the charge up signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
473	pdDnTune_1to0_2 = 0 ;//These bits control the pulse width from the phase detector into the charge down port of the charge pump. 00 turns the charge down signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
474	cpUpTune_2to0_2 = 7; //These bits control amount of current that is sourced while the charge up signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
475	cpDnTune_2to0_2 = 2; //These bits control amount of current that is sinked while the charge down signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
476	pdEn_2 = 1; //When enables, the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21. When disabled, the forceCpUp and forceCpDn settings will control the charge pump.//
477	digClkPhase_7to0_2 = 4; //Only one bit in this field should be active at one time. This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block. This is needed to control the windowing function of the DDS.//
478	Rst_n_async_2 = 0; //Digital reset//
479
480	Qg00degDelay_0to4_2 = 31; // Adjusts series delay in the 0 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
481	Qg90degDelay_0to4_2 = 7; // // Adjusts series delay in the 90 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.
482	Qg180degDelay_0to4_2 = 31; // Adjusts series delay in the 180 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
483	Qg270degDelay_0to4_2 = 7; // Adjusts series delay in the 270 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
484	DischargeTap16_3to0 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
485	ChargeTap16_3to0 = 4; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
486	DischargeTapn_3to0 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
487	ChargeTapn16_3to0 = 2; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
488	X1sel_32to39_2 = 0; // Control for the divide-by-two and x1 functions.//
489	X1sel_40to47_2 = 0 ;// Control for the divide-by-two and x1 functions.//
490	X2sel_32to36_2 = 0; // Control for the x2 function.//
491	X2sel_37to41_2 = 0; // Control for the x2 function.//
492	X4sel_32to36_2 = 0; // Control for the x4 function.//
493	X4sel_37to41_2 = 0; // Control for the x4 function.//
494	X8sel_32to36_2 = 0; // Bit 41 is used for a fine line windowing control bit. If the fine line is needed, this bit needs to be set high if Fout is close to Fref (greater than ~ 950 MHz) or for some testing modes like pass through or thru_rise_en.//
495	X8sel_41_2 = 0; // hiFout - set for passthrough and Fout close to Fref//
496	X8sel_37to40_2 = 0; // //
497	qutx_fb_180Cal_en = 0; // Enables the pad driver that sends the falling edge signal off chip. This falling edge signal is used internally to trigger the 'Reset' pin of the output RS Flip Flop.//
498	qutx_fb_0Cal_en = 0; // Enables the pad driver that sends the rising edge signal off chip. This rising edge signal is used internally to trigger the 'Set' pin of the output RS Flip Flop.//
499	qutx_fb_180Rsff_en = 0; // off//
500	qutx_fb_0Rsff_en = 0; // off//
501	// -------------------------------------------------------------------------------------------------------
502	// QuIET Dm
503	// -------------------------------------------------------------------------------------------------------
504	N = 4; // //
505	R_11to8 = 13; // //
506	R_7to0 = 172; // //
507	Asyncrst_n = 0; // off//
508	Cp_sel_6to0 = 63; // //
509	Cp_sel_8to7 = 0; // //
510	ForceFout = 0; // off//
511	ForceFoutb = 0; // off//
512	Out_en = 0; // off//
513	Dll_en = 1; // on//
514	Ana_en = 1; // off//
515
516	// -------------------------------------------------------------------------------------------------------
517	// RECEIVE QuIET FREQUENCY GENERATOR
518	// -------------------------------------------------------------------------------------------------------
519	Ngt3_3 = 0; // Output frequency control bit. Calculated.//
520	NorNdiv4_3 = 0; // Output frequency control word. Calculated.//
521	RorFrNpRdiv4_25to18_3 = 0; // Output frequency control word. Calculated.//
522	RorFrNpRdiv4_17to10_3 = 0; // //
523	RorFrNpRdiv4_9to2_3 = 0; // //
524	RorFrNpRdiv4_1to0_3 = 0; // //
525	Qu_tx_Ngt3_3 = 0; // Enables divide-by-4 freq divider - Phase shift control bit. Calculated.//
526	NorNdiv4_phsh_3 = 1; // Phase shift control word. Calculated//
527	RorFrNpRdiv4_phsh_25to18_3 = 0; // Phase shift control word. Calculated.//
528	RorFrNpRdiv4_phsh_17to10_3 = 0; // //
529	RorFrNpRdiv4_phsh_9to2_3 = 0; // //
530	RorFrNpRdiv4_phsh_1to0_3 = 0; // //
531	Passthru_ref_clk_3 = 0; // Enable reference clock pass-through mode//
532	Byp_ram_3 = 1; // Bypass the SRAMs//
533	Dis_adr_dith_3 = 1; // Disable the dither generator in the ca2adr block//
534	Dis_p5G_dith_3 = 1; // Disable the dither generator in the lup2decod block//
535	Byp_fine_3 = 1; // Bypass fine delay line control bit//
536	Exclude32_3 = 0; // Bypass fine delay line control bit (exclude 32)//
537	Dis_risedge_3 = 0; // Disable the rising edges decoders//
538	Dis_faledge_3 = 0; // Disable the falling edges decoders//
539	Spr_puls_en_3 = 0; // Enable spur pulsing mode//
540	Spr_puls_val_a_9to3_3 = 0; // Spur pulsing mode control word//
541	Spr_pulse_val_2to0_3 = 0; // //
542	Spr_puls_val_b_9to2_3 = 8; // Spur pulsing mode control word//
543	Spr_puls_val_b_1to0_3 = 0; // //
544	Thru_ris_en_3 = 0; // Put rising edges decoders into through-tap mode//
545	Thru_ris_tap_11to6_3 = 32; // Through-tap mode control word//
546	Thru_ris_tap_5to0_3 = 0; // Through-tap mode control word//
547	Thru_fal_en_3 = 0; // Put falling edges decoders into through-tap mode//
548	Thru_fal_tap_11to6_3 = 0; // Through-tap mode control word//
549	Thru_fal_tap_5to0_3 = 0; // Through-tap mode control word//
550	Dig_delay_3 = 0; // This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left offbecause the digClkPhase setting in address 23 provides much finer control.//
551	Clk_driver_en_3 = 0; // This allows the clock to reach the digital block. It first passes through the digital/analog clock synchronization mux, which means that dlEn must be on (dlEn=1) and Clk_driver=1 for the digital block to receive a clock. See Byp_fine, address 10, bit 6//
552	qu_reg_en_3 = 0; // This bit enables the voltage regulators that supply 1.2 V to all the analog block functions. There are 6 separate regulators that are simultaneously enabled by this bit.//
553	qq_reg_en_3 = 0; // This bit enables the voltage regulators that supply 1.2 V to all the Quad Gen functions. There are 3 separate regulators that are simultaneously enabled by this bit.//
554	win_rst_3 = 0; // When this bit is high, the windowing function is in a reset state, which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block.//
555	fineEn_3 = 0; // This bit, when high, routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS. When low, the coarse tap is routed directly to the output RS Flip Flop.//
556	fineEnb_3 = 0; // Opposite of fineEn.//
557	rsffEn_3 = 0; // This bit must be high to send the QuIET 0 and 180 degree calibration signals off chip. It does not control the RS Flip Flop outputs of the DDS, though it may have some second order (coupling) effect.//
558	dl_en_3 = 1; // Allows the PLL reference to enter the QuIET delay line when enabled.//
559	cp_en_3 = 1; // This bit, when enables, activates the charge pump that controls the delay line via the single pole (one capacitor) DLL loop filter.//
560	forceCpUpb_3 = 0; // This bit only matters when pdEn=0 (address 22, bit 1). When low, the pmos device connected to the DLL loop filter cap turns on and sources current into the cap, thereby increasing the delay line control voltage. //
561	forceCpDn_3 = 0; // This bit only matters when pdEn=0 (address 22, bit 1). When low, the nmos device connected to the DLL loop filter cap turns off and allows the pmos device to charge up the loop cap as described above.//
562	pdUpTune_1to0_3 = 3; // These bits control the pulse width from the phase detector into the charge up port of the charge pump. 00 turns the charge up signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
563	pdDnTune_1to0_3 = 1; // These bits control the pulse width from the phase detector into the charge down port of the charge pump. 00 turns the charge down signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
564	cpUpTune_2to0_3 = 7; // These bits control amount of current that is sourced while the charge up signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
565	cpDnTune_2to0_3 = 2; // These bits control amount of current that is sinked while the charge down signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
566	pdEn_3 = 1; // When enables, the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21. When disabled, the forceCpUp and forceCpDn settings will control the charge pump.//
567	digClkPhase_7to0_3 = 4; // Only one bit in this field should be active at one time. This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block. This is needed to control the windowing function of the DDS.//
568	Rst_n_async_3 = 0; // Digital reset.//
569	Qg00degDelay_0to4_3 = 31; // Adjusts series delay in the 0 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
570	Qg90degDelay_0to4_3 = 31; // Adjusts series delay in the 90 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
571	Qg180degDelay_0to4_3 = 31; // Adjusts series delay in the 180 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
572	Qg270degDelay_0to4_3 = 31; // Adjusts series delay in the 270 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
573	DischargeTap16_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
574	ChargeTap16_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
575	DischargeTapn_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
576	ChargeTapn16_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
577	X1sel_32to39_3 = 0; // Control for the divide-by-two and x1 functions.//
578	X1sel_40to47_3 = 0; // Control for the divide-by-two and x1 functions.//
579	X2sel_32to36_3 = 0; // Control for the x2 function.//
580	X2sel_37to41_3 = 0; // Control for the x2 function.//
581	X4sel_32to36_3 = 0; // Control for the x4 function.//
582	X4sel_37to41_3 = 0; // Control for the x4 function.//
583	X8sel_32to36_3 = 0; // Bit 41 is used for a fine line windowing control bit. If the fine line is needed, this bit needs to be set high if Fout is close to Fref (greater than ~ 950 MHz) or for some testing modes like pass through or thru_rise_en.//
584	X8sel_41_3 = 0; // hiFout - set for passthrough and Fout close to Fref//
585	X8sel_37to40_3 = 0; // //
586	qurx_180Cal_en = 0; // Enables the pad driver that sends the falling edge signal off chip. This falling edge signal is used internally to trigger the 'Reset' pin of the output RS Flip Flop.//
587	qurx_0Cal_en = 0; // Enables the pad driver that sends the rising edge signal off chip. This rising edge signal is used internally to trigger the 'Set' pin of the output RS Flip Flop.//
588	// -------------------------------------------------------------------------------------------------------
589	// PLL
590	// -------------------------------------------------------------------------------------------------------
591	extClkEn = 0; // PLL Reg 0//
592	extClkEnBNOTD7 = 1; // on//
593	div2_rst = 1; // on//
594	TxChClkSel = 0; // //
595	TxChClkEn = 0; // PLL Reg 1//
596	// -------------------------------------------------------------------------------------------------------
597	// TRANSMITTER
598	// -------------------------------------------------------------------------------------------------------
599	tx_bb_en = 0; // BB Fdbk Mux Buffer BW Control. Enables the Forward BB Reference Section of TX//
600	tx_bb_fdbk_bw = 0; // Sets the BW of the BB Correction feedback amp//
601	tx_bb_fdbk_cal_en = 0; // BB Feedback Mux path Routing. Shorts the BB Correction feedback Amp input for self-calibration//
602	tx_bb_fdbk_cart_err_en = 0; // Routes the Cartesian error signal through the BB Correction feedback//
603	tx_bb_fdbk_cart_fb_en = 0; // Routes the Cartesian feedback signal through the BB Correction feedback//
604	tx_bb_fdbk_cart_fwd_en = 0; // Routes the Cartesian reference signal through the BB Correction feedback//
605	tx_bb_fdbk_en = 0; // BB Feedback Mux path Routing. Enables the BB Correction feedback path via the RX pins//
606	tx_bb_fdbk_1q_sel = 0; // Chooses between I or Q channel for the BB Correction feedback path//
607	tx_bb_fdbk_lp = 0; // BB Fdbk Mux Buffer current. Sets the current drive capability for BB Correction feedback Amp//
608	tx_bb_fdbk_statt = 3; // BB Fdbk Mux Buffer Gain Control. BB Feedback Attenuator. Sets the voltage gain for BB Correction feedback Amp//
609	tx_bb_fdbk_swapi = 0; // Baseband Feedback Swap I & Ix. Swaps the I and Ix BB signals through the BB Correction feedback path//
610	tx_bb_fdbk_swapq = 0; // Baseband feedback Swap Q & Qx. Swaps the Q and Qx BB signal through the BB Correction feedback path//
611	tx_bb_gain_cmp = 1; // Baseband Gain 1 dB Compensation. Adds and extra 1.3 dB of Forward Baseband Reference Gain//
612	tx_bb_lp = 0; // BB ref. stage current. BB Amp Stage Current. Sets the current drive capability for Forward BB Reference Amps//
613	tx_bb_swapi = 1; // Baseband Swap I & Ix. Swaps the I and Ix BB signals through the Forward BB Reference Path//
614	tx_bb_swapq = 0; // Baseband Swap Q & Qx. Swaps the Q and Qx BB signals through the Forward BB Reference Path//
615	tx_butt_bw = 0; // BB ref. Butterworth filter BW control. Sets the BW of the Forward BB Reference 4-pole Butterworth Filters//
616	tx_bw_trck = 5; // TX MIM cap tracking filter BW. Bandwidth Tracking. Sets tracking BW of all the MIM cap based TX Filters (16 states)//
617	tx_cart_en = 0; // Cartesian FB path Enable. Enables the Cartesian Baseband Section of Tx//
618	tx_cart_fb_bb_statt = 15; // Cartesian down-mix path BB gain. Cartesian FB path BB gain. Sets the voltage gain for Cartesian BB down converter PMA//
619	tx_cart_fb_dcoc_dac_I1 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC I1//
620	tx_cart_fb_dcoc_dac_I2 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC I2//
621	tx_cart_fb_dcoc_dac_Q1 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC Q1//
622	tx_cart_fb_dcoc_dac_Q2 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC Q2//
623	CartesianFeedbackpathDCOCenable = 0; // Cartesian down-mix path BB BW//
624	CartesianFeedbackpathenable = 0; // off//
625	CartesianFBpathHiResolutionDCOCenable = 0; // off//
626	CartesianFBpathBW = 15; // //
627	CartesianFBRFGain = 0; // Cartesian down conv. path RF Gain//
628	CartesianFBpathSwapIandIx = 0; // Swap I & Ix BB in Down Converter//
629	CartesianFBpathSwapQandQx = 0; // off//
630	CartesianFBpathSwitchtoforwardSummer = 0; // off//
631	tx_cart_fb_lo_select = 0; // Cart. down conv LO curr. (tied to Gain)//
632	CartesianFBpathAmp1Gain = 3; // //
633	CartesianFBpathAmp2Gain = 3; // //
634	CartesianFBpathAmp3Gain = 3; // //
635	CartesianFBpathAmp4Gain = 3; // //
636	CartesianFBpathAmpCurrentSelect = 7; // //
637	CartesianFBpathZeroEnable = 0; // off//
638	tx_cart_zero_statt = 1; // Cartesian FB path Zero Gain. Sets the voltage gain for Cartesian Forward BB Zero Amp//
639	tx_inbuf_bw = 0; // Sets the BW of the Forward BB Reference Input Buffers//
640	tx_inbuf_statt = 0; // Sets the attenuation of the Forward BB Ref. Buffers//
641	tx_output_channel_sel = 0; // Selects from the 3 RF Forward TX output paths, 000 is full power down//
642	tx_p1_bw = 0; // Sets the BW of the Cartesian Forward BB Loop Pole 1//
643	tx_pw_bw1 = 0; // Cartesian FB path Pole 2 Bandwidth. Sets the BW of the Cartesian Forward BB Loop Pole 2//
644	tx_p2_bw2 = 0; // Cartesian FB path Pole 2 Bandwidth. Sets the BW of the Cartesian Forward BB Loop Pole 2//
645	PushPullBufferCurrent = 7; // //
646	tx_rf_aoc_bw = 0; // Sets the BW of the AOC control line//
647	RFForwardPathEnable_toMUX = 0; // off//
648	RFForwardPathEnable_ExternalPinenable = 1; // on//
649	tx_rf_fwd_lp = 0; // RF Forward Bias Reference Control. RF Forward Path Current Drain Select. Sets the current drive capability for Forward RF Output Drivers//
650	tx_rf_fwd_statt1 = 0; // RF Passive Step Attenuator control. RF Forward Path Step Attn1. Sets the attenuation level for the RF Step attenuators//
651	tx_rf_fwd_statt2 = 0; // RF Output Driver Step Attn. Control. RF Forward Path Step Attn2. Sets the attenuation level for the RF Output Drivers//
652	BBQDivideby2or4Select = 0; // BBQ Quad Gen Divide by 2 or 4 (High=1/4)//
653	BBQQuadGenEnable = 0; // Bypass Quiet LO with external LO//
654	BBQPolyphaseQuadGenEnable = 0; // off//
655	lofb_tun_s = 8; // //
656	lofb_tun_sx = 8; // //
657	lofw_tun_s2 = 8; // //
658	lofw_tun_sx2 = 8; // //
659	reserve_tx26 = 0; // //
660	reserve_tx27 = 0; // //
661	// -------------------------------------------------------------------------------------------------------
662	// RECEIVER
663	// -------------------------------------------------------------------------------------------------------
664	rx_Idac = 16; // I path DCOC DAC setting. Digital values for the DC offset adjustment. 11111 represents the maximum positive offset adjust and 00000 represents the maximum negative offset adjust. By design, codes 10000 and 01111 cause no change in the offset voltage.//
665	rx_dcs = 0; // DCOC step size select. Selects the proper current reference in the DAC to maintain constant step size at ouptut of baseband filters. This value works in tandem with the BiQuad Gain Select (address 198, bits 4:3) to maintain a constant step size of 24 mV at filter output.//
666	rx_den = 0; // Enables the DC offset correction DACs in the I and Q path.//
667	rx_Qdac = 12; // Q path DCOC DAC setting. Digital values for the DC offset adjustment. 11111 represents the maximum positive offset adjust and 00000 represents the maximum negative offset adjust. By design, codes 10000 and 01111 cause no change in the offset voltage.//
668	rx_cmpen = 0; // Enables the DC offset correction comparator used in the DCOC circuitry.//
669	rx_dcoc = 0; // Enables the DC offset correction circuitry for automatic correction of the DC offset in the baseband filters.//
670	rx_ten = 0; // Enables the RC tuning circuit to tune RX and TX baseband filters.//
671	rx_ren = 0; // Enables the ramp circuit used in the RC tuning circuitry to tune the RX and TX baseband filters.//
672	rx_dven = 0; // //
673	rx_dv = 0; // DCOC/tune clock divider select. Selects the clock rate used for clocking the DCOC and RC tuning circuit. Bits 3 and 2 set the divider setting used for both the DCOC circuitry and RC Tune circuitry. Bits 1 and 0 set the divider setting for the dedicated divider in the DCOC circuitry. Table below shows the mapping of divider settings. The DCOC clock divider setting is the total divide ratio of both dividers. The maximum divide ratio is 8*8 = 64.//
674	rx_extc = 0; // Enables the external capacitor pins to allow for external low-frequency pole to be placed in the signal path between the mixer and baseband filter.//
675	rx_cen = 0; // Chopper enable for filter stages. Settings to enable which amplifier the clock is being applied//
676	rx_chck = 0; // Divider setting for the chopper clock//
677	rx_chcken = 0; // Enables the baseband filter chopper clock.//
678	rx_fen = 0; // Enables baseband filters. 0 puts filter in power save mode.//
679	rx_onchen = 0; // Enables on-channel detector.//
680	rx_offchen = 0; // Enables off-channel detector//
681	rx_foe = 0; // Enables the output of the baseband filters. Otherwise the baseband filter outputs are in a Hi-Z state to allow transmitter to use filter output pins. When Filter Enable is set LOW, outputs are disabled (Hi-Z)//
682	rx_offch = 1; // Sets the Clip Threshold for the Off-channel Detector//
683	rx_onchf = 0; // Sets the Fade Threshold for the On-channel Detector relative to the On-channel clip point.//
684	rx_onchc = 2 ;// Sets the Clip Threshold for the On-channel Detector//
685	rx_qs = 0; // Sets the BiQuad filter Q//
686	rx_bqg = 0; // Set BiQuad filter gain//
687	// FIXME Maybe set rx_rq to 0
688	rx_rq = 1; // Sets the BiQuad filter resistor value. The natural frequency of the BiQuad (wo) is this resistor value multiplied by the BiQuad Capacitor value.//
689	rx_rv = 1; // Sets the VGA filter (passive filter) resistor value. The pole frequency of the passive filter is this resistor value multiplied by the VGA capacitor value.//
690	rx_rip = 0; // Sets the MPA input resistor value that sets the gain of the PMA. Gain of the PMA is Rf/Rin where Rf is the PMA feedback resistor and Rin is the input resistor. Note that the input resistance remains at 2 kohm differential for all settings. An R2R ladder is used to accomplish this while changing the Rin value.//
691	rx_rfp = 2; // Sets the PMA feedback resistor value that sets the gain of the PMA as well as the pole frequency (along with PMA capacitor value). Gain of the PMA is Rf/Rin where Rf is the PMA feedback resistor and Rin is the input resistor.//
692	rx_cp_12to8 = 0; // Sets the PMA filter capacitor value. The pole frequency of the PMA filter is the PMA feedback resistor value multiplied by this Capacitor value. PMA Capacitor (in pF) = (PMAC) * 0.0625 + 1//
693	rx_gs = 0; // Sets the gain of the VGA in the baseband filter//
694	rx_cp_7to0 = 0; // PMA cap select LSBs. Sets the PMA filter capacitor value. The pole frequency of the PMA filter is the PMA feedback resistor value multiplied by this Capacitor value. PMA Capacitor (in pF) = (PMAC) * 0.0625 + 1//
695	rx_cv_10to3 = 0; // VGA cap select MSBs. Sets the VGA (passive) filter capacitor value. This pole frequency of the passive filter is the VGA resistor value multiplied by this Capacitor value. VGA Capacitor (in pF) = (VGAC) * 0.0625 + 1//
696	rx_cv_2to0 = 0; // VGA cap select LSBs. Sets the VGA (passive) filter capacitor value. This pole frequency of the passive filter is the VGA resistor value multiplied by this Capacitor value. VGA Capacitor (in pF) = (VGAC) * 0.0625 + 1//
697	rx_cc_2to0 = 0; // Compensation control. Disables additional compensation capacitance in the VGA and BiQuad op-amps to allow for higher bandwidths. Also increases the op-ampdominate pole-frequency which improves filter response. Bit 4 controls the VGA amplifier, Bit 3 controls the feedback amplifier in the BiQuad, and Bit 2 controls the output buffer in the BiQuad.//
698	rx_cq_9to8 = 0; // BiQuad cap select MSBs. Sets the BiQuad filter capacitor value. The natural frequency of the BiQuad (wo) is the BiQuad resistor value multiplied by this Capacitor value. BiQuad Capacitor (in pF) = (BiQuadC) * 0.125 + 2//
699	rx_cq_7to0 = 0; // BiQuad cap select LSBs. Sets the BiQuad filter capacitor value. The natural frequency of the BiQuad (wo) is the BiQuad resistor value multiplied by this Capacitor value. BiQuad Capacitor (in pF) = (BiQuadC) * 0.125 + 2//
700	rx_lna = 1; // LNA select//
701	rx_lnab = 0; // LNA bias select//
702	rx_rxchen = 0; // RX mixer enable. Must be set to 1 to enable Mixer operation//
703	rx_bbq_div2or4 = 0; // Selects divide ratio of RX Quad Gen when using external LO. 0->DIV2, 1 ->DIV1//
704	rx_Loselect = 0; // RX external LO select. Enables external LO clock source//
705	poly_en = 0; // off//
706	lorx_tun_s = 8; // //
707	lorx_tun_sx = 8; // //
708
709	shft_cml_in = 0; //Enable - 150mV level shift of Ref. BB VAG//
710	vagenable1 = 1; //Enable VAG Gen into Sleep Mode (slow ramp up)//
711	vagenable2 = 1; //Enable VAG Gen in Full On Mode (Fast ramp from sleep)//
712	//-------------------------------------------------------------------------------------------------------
713	// TEST MULTIPLEXER
714	//-------------------------------------------------------------------------------------------------------
715	TestMuxBufferEnable = 0; //Enable Test Mux Buffer//
716	TestMuxEnable = 0; //Enable Test Mux//
717	TestMuxSetting = 0; //Four Output Description (Test1, Test2, Test3, Test4)//
718	txgain = 0; //Set Transmit Gain//
719	Fclk = 1000e6; //Default clock frequency, in Hz//
720
721	Fouttx = 0; // Default tx frequency is zero//
722	Foutrx = 0; // Default rx frequency is zero//
723	Foutfb = 0; // Default feedback frequency is zero//
724
725	// Initialize GPIO and ATR
726	// GPIO are the general-purpose IO pins on the daughterboard
727	// IO_RX_06 must be used for ATR (1 = TX, 0 = RX)
728	// ATR is the automatic transmit/receive switching, done in the FPGA
729	// FIXME
730
731
732	rx_write_io(0, TX_EN);
733	rx_write_oe(TX_EN, TX_EN);
734	rx_set_atr_rxval(0);
735	rx_set_atr_txval(TX_EN);
736	rx_set_atr_mask(TX_EN);
737
738	d_spi_format = SPI_FMT_MSB \| SPI_FMT_HDR_2;
739	d_spi_format_no_header = SPI_FMT_MSB \| SPI_FMT_HDR_0;
740
741	if (int(which) == 0)
742	d_spi_enable = SPI_ENABLE_RX_A;
743	else
744	d_spi_enable = SPI_ENABLE_RX_B;
745
746	set_reg_96();
747	set_reg_97();
748	set_reg_98();
749	set_reg_99();
750
751	set_reg_152();
752	set_reg_153();
753
754	set_reg_220();
755	set_reg_222();
756
757
758
759	}
760
761	rfic::~rfic()
762	{
763	//printf("rfic::destructor\n");
764	shutdown();
765	}
766
767	void
768	rfic::shutdown()
769	{
770	Rst_n_async = 0;
771	set_reg_24();
772	Rst_n_async2 = 0;
773	set_reg_72();
774	Rst_n_async3 = 0;
775	set_reg_128();
776
777	X1sel_32to39_3 = 0;
778	X1sel_40to47_3 = 0;
779	X2sel_32to36_3 = 0;
780	X2sel_37to41_3 = 0;
781	X4sel_32to36_3 = 0;
782	X4sel_37to41_3 = 0;
783
784	set_reg_139();
785	set_reg_140();
786	set_reg_141();
787	set_reg_142();
788	set_reg_143();
789	set_reg_144();
790
791	X1sel_32to39 = 0;
792	X1sel_40to47 = 0;
793	X2sel_32to36 = 0;
794	X2sel_37to41 = 0;
795	X4sel_32to36 = 0;
796	X4sel_37to41 = 0;
797
798	set_reg_35();
799	set_reg_36();
800	set_reg_37();
801	set_reg_38();
802	set_reg_39();
803	set_reg_40();
804
805	X1sel_32to39_2 = 0;
806	X1sel_40to47_2 = 0;
807	X2sel_32to36_2 = 0;
808	X2sel_37to41_2 = 0;
809	X4sel_32to36_2 = 0;
810	X4sel_37to41_2 = 0;
811
812	set_reg_83();
813	set_reg_84();
814	set_reg_85();
815	set_reg_86();
816	set_reg_87();
817	set_reg_88();
818
819	// --------------------------------------------------------------------
820	// These methods set the RFIC onboard registers over the SPI bus.
821	// Thus, the shift values here are the 0-7 values from the data sheet
822
823	// For more information about setting each variable and SPI register, see RFIC4 SPI Default Variables.xls
824
825
826	///////////////////////////////////have to do this after i finish all the set reg functions///////////////////////////////////
827	}
828
829	bool
830	rfic::rx_write_oe(int value,int mask){
831
832	if (int(d_which) == 0)
833	return usrp()->_write_fpga_reg(FR_OE_1, (mask << 16) \| value);
834	else
835	return usrp()->_write_fpga_reg(FR_OE_3, (mask << 16) \| value);
836	}
837
838	bool
839	rfic::rx_write_io(int value,int mask){
840
841	if (int(d_which) == 0)
842	return usrp()->_write_fpga_reg(FR_IO_1, (mask << 16) \| value);
843	else
844	return usrp()->_write_fpga_reg(FR_IO_3, (mask << 16) \| value);
845
846	}
847
848	bool
849	rfic::rx_set_atr_mask(int value){
850
851	if (int(d_which) == 0)
852	return usrp()->_write_fpga_reg(FR_ATR_MASK_1, value);
853	else
854	return usrp()->_write_fpga_reg(FR_ATR_MASK_3, value);
855
856	}
857
858	bool
859	rfic::rx_set_atr_txval(int value){
860
861	if (int(d_which) == 0)
862	return usrp()->_write_fpga_reg(FR_ATR_TXVAL_1, value);
863	else
864	return usrp()->_write_fpga_reg(FR_ATR_TXVAL_3, value);
865	}
866
867	bool
868	rfic::rx_set_atr_rxval(int value){
869
870	if (int(d_which) == 0)
871	return usrp()->_write_fpga_reg(FR_ATR_RXVAL_1, value);
872	else
873	return usrp()->_write_fpga_reg(FR_ATR_RXVAL_3, value);
874
875	}
876
877
878
879
880
881
882	void
883	rfic::send_reg(int reg_no,int dat )
884	{
885
886	// dat is the data to write to register 0
887	//spi_enable is the spi enables
888	//spi_format is the spi format with a two-byte header
889	//spi_format_no_header is the spi format, with no header
890	//Send 16 bit header over SPI to send register number
891	//Write 8 bit register
892	//Set header
893
894	std::cout<<"db_rfic.cc: Register no: "<<reg_no<<" ,Value: "<<dat<<std::endl;
895	//std::cout<<"db_rfic.cc:Value on the register before writing"<<get_reg(reg_no)<<std::endl;
896
897	int hdr = int((reg_no << 1) & 0x7fff); //since the 14 bit address lies from bits 1-14..0th bit is for auto increment..15th bit is for read/write
898	char c[1];
899	c[0] = (char)(dat&0xff);
900	std::string s(c, 1); //s is the data to be sent to the register
901
902	bool check;
903
904	check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, s);
905	//if (check)
906	//std::cout<<"db_rfic.cc: Write successful"<<std::endl; //Do not trust variable check!
907	//else
908	//std::cout<<"db_rfic.cc: Write failed"<<std::endl;
909	//std::cout<<"db_rfic.cc:Value on the register after ****** writing\n "<<get_reg(reg_no)<<"**"<<std::endl;
910	//if(reg_no == 60)
911	//get_reg(reg_no);
912	}
913
914	char
915	rfic::get_reg(int reg_num)
916	{
917
918	//Returns a vector containing the information in the first 320 registers in integer form
919	//dat is the data to write to register 0
920	//spi_enable is the spi enables
921	//spi_format is the spi format with a two-byte header
922	//spi_format_no_header is the spi format, with no header
923	//u is the instance of the USRP
924
925	int hdr = 0;
926	int dat = 0;
927	char c[1];
928	c[0] = (char)(dat&0xff);
929	std::string s(c, 1); //s is the data to be sent to the register
930
931	bool check;
932	check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, s);
933
934	std::string r; //string to be read from the register
935	r = usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); //Starts reading from register 0 since the previous write is on register 0
936	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
937	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
938	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
939	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
940	std::cout<<"db_rfic.cc: contents of all registers \n*"<<r<<"*"<<std::endl;
941	char read_val = (char)r[reg_num];
942	return read_val;
943	}
944
945	void rfic :: set_reg_205(){
946	int reg_205 = (
947	rx_lna << 5 \|
948	rx_lnab << 3 \|
949	rx_rxchen << 2 \|
950	rx_bbq_div2or4 << 1 \|
951	rx_Loselect << 0 );
952	send_reg(205, reg_205);
953	}
954
955	void rfic :: set_reg_0(){
956	int reg_0 = (
957	Ngt3 << 7 \|
958	NorNdiv4 << 0 );
959	send_reg(0, reg_0);
960	}
961
962	void rfic :: set_reg_1(){
963	int reg_1 = (
964	RorFrNpRdiv4_25to18 << 0 );
965	send_reg(1, reg_1);
966	}
967
968
969	void rfic :: set_reg_2(){
970	int reg_2 = (
971	RorFrNpRdiv4_17to10 << 0 );
972	send_reg(2, reg_2);
973	}
974
975	void rfic :: set_reg_3(){
976	int reg_3 = (
977	RorFrNpRdiv4_9to2 << 0 );
978	send_reg(3, reg_3);
979	}
980
981
982	void rfic :: set_reg_4(){
983	int reg_4 = (
984	RorFrNpRdiv4_1to0 << 6 );
985	send_reg(4, reg_4);
986	}
987	void rfic :: set_reg_5(){
988	int reg_5 = (
989	Qu_tx_Ngt3 << 7 \|
990	NorNdiv4_phsh << 0 );
991	send_reg(5, reg_5);
992	}
993
994	void rfic :: set_reg_6(){
995	int reg_6 = (
996	RorFrNpRdiv4_phsh_25to18 << 0 );
997	send_reg(6, reg_6);
998	}
999
1000	void rfic :: set_reg_7(){
1001	int reg_7 = (
1002	RorFrNpRdiv4_phsh_17to10 << 0 );
1003	send_reg(7, reg_7);
1004	}
1005
1006	void rfic :: set_reg_8(){
1007	int reg_8 = (
1008	RorFrNpRdiv4_phsh_9to2 << 0 );
1009	send_reg(8, reg_8);
1010	}
1011
1012	void rfic :: set_reg_9(){
1013	int reg_9 = (
1014	RorFrNpRdiv4_phsh_1to0 << 6 );
1015	send_reg(9, reg_9);
1016	}
1017
1018	void rfic :: set_reg_10(){
1019	int reg_10 = (
1020	Passthru_ref_clk << 7 \|
1021	Byp_ram << 6 \|
1022	Dis_adr_dith << 5 \|
1023	Dis_p5G_dith << 4 \|
1024	Byp_fine << 3 \|
1025	Exclude32 << 2 \|
1026	Dis_risedge << 1 \|
1027	Dis_faledge << 0 );
1028	send_reg(10, reg_10);
1029	}
1030
1031
1032	void rfic :: set_reg_12(){
1033	int reg_12 = (
1034	Spr_puls_en << 7 \|
1035	Spr_puls_val_a_9to3 << 0 );
1036	send_reg(12, reg_12);
1037	}
1038
1039	void rfic :: set_reg_13(){
1040	int reg_13 = (
1041	Spr_pulse_val_2to0 << 5 );
1042	send_reg(13, reg_13);
1043	}
1044
1045	void rfic :: set_reg_14(){
1046	int reg_14 = (
1047	Spr_puls_val_b_9to2 << 0 );
1048	send_reg(14, reg_14);
1049	}
1050
1051	void rfic :: set_reg_15(){
1052	int reg_15 = (
1053	Spr_puls_val_b_1to0 << 6 );
1054	send_reg(15, reg_15);
1055	}
1056
1057
1058	void rfic :: set_reg_16(){
1059	int reg_16 = (
1060	Thru_ris_en << 7 \|
1061	Thru_ris_tap_11to6 << 1 );
1062	send_reg(16, reg_16);
1063	}
1064
1065	void rfic :: set_reg_17(){
1066	int reg_17 = (
1067	Thru_ris_tap_5to0 << 2 );
1068	send_reg(17, reg_17);
1069	}
1070
1071	void rfic :: set_reg_18(){
1072	int reg_18 = (
1073	Thru_fal_en << 7 \|
1074	Thru_fal_tap_11to6 << 1 );
1075	send_reg(18, reg_18);
1076	}
1077	void rfic :: set_reg_19(){
1078	int reg_19 = (
1079	Thru_fal_tap_5to0 << 2 );
1080	send_reg(19, reg_19);
1081	}
1082	void rfic :: set_reg_20(){
1083	int reg_20 = (
1084	Dig_delay << 7 \|
1085	Clk_driver_en << 6 \|
1086	qu_reg_en << 5 \|
1087	qq_reg_en << 4 \|
1088	win_rst << 3 \|
1089	fineEn << 2 \|
1090	fineEnb << 1 \|
1091	rsffEn << 0 );
1092	send_reg(20, reg_20);
1093	}
1094
1095	void rfic :: set_reg_21(){
1096	int reg_21 = (
1097	dl_en << 7 \|
1098	cp_en << 6 \|
1099	forceCpUpb << 5 \|
1100	forceCpDn << 4 \|
1101	pdUpTune_1to0 << 2 \|
1102	pdDnTune_1to0 << 0 );
1103	send_reg(21, reg_21);
1104	}
1105
1106	void rfic :: set_reg_22(){
1107	int reg_22 = (
1108	cpUpTune_2to0 << 5 \|
1109	cpDnTune_2to0 << 2 \|
1110	pdEn << 1 );
1111	send_reg(22, reg_22);
1112	}
1113
1114	void rfic :: set_reg_23(){
1115	int reg_23 = (
1116	digClkPhase_7to0 << 0 );
1117	send_reg(23, reg_23);
1118	}
1119	void rfic :: set_reg_24(){
1120	int reg_24 = (
1121	Rst_n_async << 7 );
1122	send_reg(24, reg_24);
1123	}
1124	void rfic :: read_reg_25(){
1125	int reg_25 = get_reg(25);
1126	L1_lup00_15to8 = reg_25;
1127	}
1128	void rfic :: read_reg_26(){
1129	int reg_26 = get_reg(26);
1130	L1_lup90_15to8 = reg_26;
1131	}
1132	void rfic :: read_reg_27(){
1133	int reg_27 = get_reg(27);
1134	Merg_ris_fin = reg_27 >> 2;
1135	}
1136	void rfic :: read_reg_28(){
1137	int reg_28 = get_reg(28);
1138	Merg_fal_fin = reg_28 >> 2;
1139	}
1140	void rfic :: set_reg_29(){
1141	int reg_29 = (
1142	Qg00degDelay_0to4 << 3 );
1143	send_reg(29, reg_29);
1144	}
1145	void rfic :: set_reg_30(){
1146	int reg_30 = (
1147	Qg90degDelay_0to4 << 3 );
1148	send_reg(30, reg_30);
1149	}
1150	void rfic :: set_reg_31(){
1151	int reg_31 = (
1152	Qg180degDelay_0to4 << 3 );
1153	send_reg(31, reg_31);
1154	}
1155	void rfic :: set_reg_32(){
1156	int reg_32 = (
1157	Qg270degDelay_0to4 << 3 );
1158	send_reg(32, reg_32);
1159	}
1160	void rfic :: set_reg_33(){
1161	int reg_33 = (
1162	DischargeTap16_0to3 << 4 \|
1163	ChargeTap16_0to3 << 0 );
1164	send_reg(33, reg_33);
1165	}
1166	void rfic :: set_reg_34(){
1167	int reg_34 = (
1168	DischargeTapn_0to3 << 4 \|
1169	ChargeTapn16_0to3 << 0 );
1170	send_reg(34, reg_34);
1171	}
1172	void rfic :: set_reg_35(){
1173	int reg_35 = (
1174	X1sel_32to39 << 0 );
1175	send_reg(35, reg_35);
1176	}
1177	void rfic :: set_reg_36(){
1178	int reg_36 = (
1179	X1sel_40to47 << 0 );
1180	send_reg(36, reg_36);
1181	}
1182	void rfic :: set_reg_37(){
1183	int reg_37 = (
1184	X2sel_32to36 << 3 );
1185	send_reg(37, reg_37);
1186	}
1187	void rfic :: set_reg_38(){
1188	int reg_38 = (
1189	X2sel_37to41 << 3 );
1190	send_reg(38, reg_38);
1191	}
1192	void rfic :: set_reg_39(){
1193	int reg_39 = (
1194	X4sel_32to36 << 3 );
1195	send_reg(39, reg_39);
1196	}
1197	void rfic :: set_reg_40(){
1198	int reg_40 = (
1199	X4sel_37to41 << 3 );
1200	send_reg(40, reg_40);
1201	}
1202	void rfic :: set_reg_41(){
1203	int reg_41 = (
1204	X8sel_32to36 << 3 );
1205	send_reg(41, reg_41);
1206	}
1207	void rfic :: set_reg_42(){
1208	int reg_42 = (
1209	X8sel_41 << 7 \|
1210	X8sel_37to40 << 3 );
1211	send_reg(42, reg_42);
1212	}
1213	void rfic :: set_reg_43(){
1214	int reg_43 = (
1215	qutx_fwd_180Cal_en << 7 \|
1216	qutx_fwd_0Cal_en << 6 );
1217	send_reg(43, reg_43);
1218	}
1219	void rfic :: set_reg_48(){
1220	int reg_48 = (
1221	Ngt3_2 << 7 \|
1222	NorNdiv4_2 << 0 );
1223	send_reg(48, reg_48);
1224	}
1225	void rfic :: set_reg_49(){
1226	int reg_49 = (
1227	RorFrNpRdiv4_25to18_2 << 0 );
1228	send_reg(49, reg_49);
1229	}
1230	void rfic :: set_reg_50(){
1231	int reg_50 = (
1232	RorFrNpRdiv4_17to10_2 << 0 );
1233	send_reg(50, reg_50);
1234	}
1235	void rfic :: set_reg_51(){
1236	int reg_51 = (
1237	RorFrNpRdiv4_9to2_2 << 0 );
1238	send_reg(51, reg_51);
1239	}
1240	void rfic :: set_reg_52(){
1241	int reg_52 = (
1242	RorFrNpRdiv4_1to0_2 << 6 );
1243	send_reg(52, reg_52);
1244	}
1245	void rfic :: set_reg_53(){
1246	int reg_53 = (
1247	Qu_tx_Ngt3_2 << 7 \|
1248	NorNdiv4_phsh_2 << 0 );
1249	send_reg(52, reg_53);
1250	}
1251	void rfic :: set_reg_54(){
1252	int reg_54 = (
1253	RorFrNpRdiv4_phsh_25to18_2 << 0 );
1254	send_reg(54, reg_54);
1255	}
1256	void rfic :: set_reg_55(){
1257	int reg_55 = (
1258	RorFrNpRdiv4_phsh_17to10_2 << 0 );
1259	send_reg(55, reg_55);
1260	}
1261	void rfic :: set_reg_56(){
1262	int reg_56 = (
1263	RorFrNpRdiv4_phsh_9to2_2 << 0 );
1264	send_reg(56, reg_56);
1265	}
1266	void rfic :: set_reg_57(){
1267	int reg_57 = (
1268	RorFrNpRdiv4_phsh_1to0_2 << 6 );
1269	send_reg(57, reg_57);
1270	}
1271	void rfic :: set_reg_58(){
1272	int reg_58 = (
1273	Passthru_ref_clk_2 << 7 \|
1274	Byp_ram_2 << 6 \|
1275	Dis_adr_dith_2 << 5 \|
1276	Dis_p5G_dith_2 << 4 \|
1277	Byp_fine_2 << 3 \|
1278	Exclude32_2 << 2 \|
1279	Dis_risedge_2 << 1 \|
1280	Dis_faledge_2 << 0 );
1281	send_reg(58, reg_58);
1282	}
1283	void rfic :: set_reg_60(){
1284	int reg_60 = (
1285	Spr_puls_en_2 << 7 \|
1286	Spr_puls_val_a_9to3_2 << 0 );
1287	send_reg(60, reg_60);
1288	}
1289	void rfic :: set_reg_61(){
1290	int reg_61 = (
1291	Spr_pulse_val_2to0_2 << 5 );
1292	send_reg(61, reg_61);
1293	}
1294	void rfic :: set_reg_62(){
1295	int reg_62 = (
1296	Spr_puls_val_b_9to2_2 << 0 );
1297	send_reg(62, reg_62);
1298	}
1299	void rfic :: set_reg_63(){
1300	int reg_63 = (
1301	Spr_puls_val_b_1to0_2 << 6 );
1302	send_reg(63, reg_63);
1303	}
1304	void rfic :: set_reg_64(){
1305	int reg_64 = (
1306	Thru_ris_en_2 << 7 \|
1307	Thru_ris_tap_11to6_2 << 1 );
1308	send_reg(64, reg_64);
1309	}
1310	void rfic :: set_reg_65(){
1311	int reg_65 = (
1312	Thru_ris_tap_5to0_2 << 2 );
1313	send_reg(65, reg_65);
1314	}
1315	void rfic :: set_reg_66(){
1316	int reg_66 = (
1317	Thru_fal_en_2 << 7 \|
1318	Thru_fal_tap_11to6_2 << 1 );
1319	send_reg(66, reg_66);
1320	}
1321	void rfic :: set_reg_67(){
1322	int reg_67 = (
1323	Thru_fal_tap_5to0_2 << 2 );
1324	send_reg(67, reg_67);
1325	}
1326	void rfic :: set_reg_68(){
1327	int reg_68 = (
1328	Dig_delay_2 << 7 \|
1329	Clk_driver_en_2 << 6 \|
1330	qu_reg_en_2 << 5 \|
1331	qq_reg_en_2 << 4 \|
1332	win_rst_2 << 3 \|
1333	fineEn_2 << 2 \|
1334	fineEnb_2 << 1 \|
1335	rsffEn_2 << 0 );
1336	send_reg(68, reg_68);
1337	}
1338	void rfic :: set_reg_69(){
1339	int reg_69 = (
1340	dl_en_2 << 7 \|
1341	cp_en_2 << 6 \|
1342	forceCpUpb_2 << 5 \|
1343	forceCpDn_2 << 4 \|
1344	pdUpTune_1to0_2 << 2 \|
1345	pdDnTune_1to0_2 << 0 );
1346	send_reg(69, reg_69);
1347	}
1348	void rfic :: set_reg_70(){
1349	int reg_70 = (
1350	cpUpTune_2to0_2 << 5 \|
1351	cpDnTune_2to0_2 << 2 \|
1352	pdEn_2 << 1 );
1353	send_reg(70, reg_70);
1354	}
1355	void rfic :: set_reg_71(){
1356	int reg_71 = (
1357	digClkPhase_7to0_2 << 0 );
1358	send_reg(71, reg_71);
1359	}
1360	void rfic :: set_reg_72(){
1361	int reg_72 = (
1362	Rst_n_async_2 << 7 );
1363	send_reg(72, reg_72);
1364	}
1365	void rfic :: read_reg_73(){
1366	int reg_73 = get_reg(73);
1367	L1_lup00_15to8_2 = reg_73;
1368	}
1369	void rfic :: read_reg_74(){
1370	int reg_74 = get_reg(74);
1371	L1_lup90_15to8_2 = reg_74;
1372	}
1373	void rfic :: read_reg_75(){
1374	int reg_75 = get_reg(75);
1375	Merg_ris_fin_2 = reg_75 >> 2;
1376	}
1377	void rfic :: read_reg_76(){
1378	int reg_76 = get_reg(76);
1379	Merg_fal_fin_2 = reg_76 >> 2;
1380	}
1381	void rfic :: set_reg_77(){
1382	int reg_77 = (
1383	Qg00degDelay_0to4_2 << 3 );
1384	send_reg(77, reg_77);
1385	}
1386	void rfic :: set_reg_78(){
1387	int reg_78 = (
1388	Qg90degDelay_0to4_2 << 3 );
1389	send_reg(78, reg_78);
1390	}
1391	void rfic :: set_reg_79(){
1392	int reg_79 = (
1393	Qg180degDelay_0to4_2 << 3 );
1394	send_reg(79, reg_79);
1395	}
1396	void rfic :: set_reg_80(){
1397	int reg_80 = (
1398	Qg270degDelay_0to4_2 << 3 );
1399	send_reg(80, reg_80);
1400	}
1401	void rfic :: set_reg_81(){
1402	int reg_81 = (
1403	DischargeTap16_3to0 << 4 \|
1404	ChargeTap16_3to0 << 0 );
1405	send_reg(81, reg_81);
1406	}
1407	void rfic :: set_reg_82(){
1408	int reg_82 = (
1409	DischargeTapn_3to0 << 4 \|
1410	ChargeTapn16_3to0 << 0 );
1411	send_reg(82, reg_82);
1412	}
1413	void rfic :: set_reg_83(){
1414	int reg_83 = (
1415	X1sel_32to39_2 << 0 );
1416	send_reg(83, reg_83);
1417	}
1418	void rfic :: set_reg_84(){
1419	int reg_84 = (
1420	X1sel_40to47_2 << 0 );
1421	send_reg(84, reg_84);
1422	}
1423	void rfic :: set_reg_85(){
1424	int reg_85 = (
1425	X2sel_32to36_2 << 3 );
1426	send_reg(85, reg_85);
1427	}
1428	void rfic :: set_reg_86(){
1429	int reg_86 = (
1430	X2sel_37to41_2 << 3 );
1431	send_reg(86, reg_86);
1432	}
1433	void rfic :: set_reg_87(){
1434	int reg_87 = (
1435	X4sel_32to36_2 << 3 );
1436	send_reg(87, reg_87);
1437	}
1438	void rfic :: set_reg_88(){
1439	int reg_88 = (
1440	X4sel_37to41_2 << 3 );
1441	send_reg(88, reg_88);
1442	}
1443	void rfic :: set_reg_89(){
1444	int reg_89 = (
1445	X8sel_32to36_2 << 3 );
1446	send_reg(89, reg_89);
1447	}
1448	void rfic :: set_reg_90(){
1449	int reg_90 = (
1450	X8sel_41_2 << 7 \|
1451	X8sel_37to40_2 << 3 );
1452	send_reg(90, reg_90);
1453	}
1454	void rfic :: set_reg_91(){
1455	int reg_91 = (
1456	qutx_fb_180Cal_en << 7 \|
1457	qutx_fb_0Cal_en << 6 \|
1458	qutx_fb_180Rsff_en << 5 \|
1459	qutx_fb_0Rsff_en << 4 );
1460	send_reg(91, reg_91);
1461	}
1462	void rfic :: set_reg_96(){
1463	int reg_96 = (
1464	N << 4 \|
1465	R_11to8 << 0 );
1466	send_reg(96, reg_96);
1467	}
1468	void rfic :: set_reg_97(){
1469	int reg_97 = (
1470	R_7to0 << 0 );
1471	send_reg(97, reg_97);
1472	}
1473	void rfic :: set_reg_98(){
1474	int reg_98 = (
1475	Asyncrst_n << 7 \|
1476	Cp_sel_6to0 << 0 );
1477	send_reg(98, reg_98);
1478	}
1479	void rfic :: set_reg_99(){
1480	int reg_99 = (
1481	Cp_sel_8to7 << 6 \|
1482	ForceFout << 5 \|
1483	ForceFoutb << 4 \|
1484	Out_en << 3 \|
1485	Dll_en << 2 \|
1486	Ana_en << 1 );
1487	send_reg(99, reg_99);
1488	}
1489	void rfic :: read_reg_100(){
1490	int reg_100 = get_reg(100);
1491	Decod_in_0deg = reg_100 >> 3;
1492	}
1493	void rfic :: set_reg_104(){
1494	int reg_104 = (
1495	Ngt3_3 << 7 \|
1496	NorNdiv4_3 << 0 );
1497	send_reg(104, reg_104);
1498	}
1499	void rfic :: set_reg_105(){
1500	int reg_105 = (
1501	RorFrNpRdiv4_25to18_3 << 0 );
1502	send_reg(105, reg_105);
1503	}
1504	void rfic :: set_reg_106(){
1505	int reg_106 = (
1506	RorFrNpRdiv4_17to10_3 << 0 );
1507	send_reg(106, reg_106);
1508	}
1509	void rfic :: set_reg_107(){
1510	int reg_107 = (
1511	RorFrNpRdiv4_9to2_3 << 0 );
1512	send_reg(107, reg_107);
1513	}
1514	void rfic :: set_reg_108(){
1515	int reg_108 = (
1516	RorFrNpRdiv4_1to0_3 << 6 );
1517	send_reg(108, reg_108);
1518	}
1519	void rfic :: set_reg_109(){
1520	int reg_109 = (
1521	Qu_tx_Ngt3_3 << 7 \|
1522	NorNdiv4_phsh_3 << 0 );
1523	send_reg(109, reg_109);
1524	}
1525	void rfic :: set_reg_110(){
1526	int reg_110 = (
1527	RorFrNpRdiv4_phsh_25to18_3 << 0 );
1528	send_reg(110, reg_110);
1529	}
1530	void rfic :: set_reg_111(){
1531	int reg_111 = (
1532	RorFrNpRdiv4_phsh_17to10_3 << 0 );
1533	send_reg(111, reg_111);
1534	}
1535	void rfic :: set_reg_112(){
1536	int reg_112 = (
1537	RorFrNpRdiv4_phsh_9to2_3 << 0 );
1538	send_reg(112, reg_112);
1539	}
1540	void rfic :: set_reg_113(){
1541	int reg_113 = (
1542	RorFrNpRdiv4_phsh_1to0_3 << 6 );
1543	send_reg(113, reg_113);
1544	}
1545	void rfic :: set_reg_114(){
1546	int reg_114 = (
1547	Passthru_ref_clk_3 << 7 \|
1548	Byp_ram_3 << 6 \|
1549	Dis_adr_dith_3 << 5 \|
1550	Dis_p5G_dith_3 << 4 \|
1551	Byp_fine_3 << 3 \|
1552	Exclude32_3 << 2 \|
1553	Dis_risedge_3 << 1 \|
1554	Dis_faledge_3 << 0 );
1555	send_reg(114, reg_114);
1556	}
1557	void rfic :: set_reg_116(){
1558	int reg_116 = (
1559	Spr_puls_en_3 << 7 \|
1560	Spr_puls_val_a_9to3_3 << 0 );
1561	send_reg(116, reg_116);
1562	}
1563	void rfic :: set_reg_117(){
1564	int reg_117 = (
1565	Spr_pulse_val_2to0_3 << 5 );
1566	send_reg(117, reg_117);
1567	}
1568	void rfic :: set_reg_118(){
1569	int reg_118 = (
1570	Spr_puls_val_b_9to2_3 << 0 );
1571	send_reg(118, reg_118);
1572	}
1573	void rfic :: set_reg_119(){
1574	int reg_119 = (
1575	Spr_puls_val_b_1to0_3 << 6 );
1576	send_reg(119, reg_119);
1577	}
1578	void rfic :: set_reg_120(){
1579	int reg_120 = (
1580	Thru_ris_en_3 << 7 \|
1581	Thru_ris_tap_11to6_3 << 1 );
1582	send_reg(120, reg_120);
1583	}
1584	void rfic :: set_reg_121(){
1585	int reg_121 = (
1586	Thru_ris_tap_5to0_3 << 2 );
1587	send_reg(121, reg_121);
1588	}
1589	void rfic :: set_reg_122(){
1590	int reg_122 = (
1591	Thru_fal_en_3 << 7 \|
1592	Thru_fal_tap_11to6_3 << 1 );
1593	send_reg(122, reg_122);
1594	}
1595	void rfic :: set_reg_123(){
1596	int reg_123 = (
1597	Thru_fal_tap_5to0_3 << 2 );
1598	send_reg(123, reg_123);
1599	}
1600	void rfic :: set_reg_124(){
1601	int reg_124 = (
1602	Dig_delay_3 << 7 \|
1603	Clk_driver_en_3 << 6 \|
1604	qu_reg_en_3 << 5 \|
1605	qq_reg_en_3 << 4 \|
1606	win_rst_3 << 3 \|
1607	fineEn_3 << 2 \|
1608	fineEnb_3 << 1 \|
1609	rsffEn_3 << 0 );
1610	send_reg(124, reg_124);
1611	}
1612	void rfic :: set_reg_125(){
1613	int reg_125 = (
1614	dl_en_3 << 7 \|
1615	cp_en_3 << 6 \|
1616	forceCpUpb_3 << 5 \|
1617	forceCpDn_3 << 4 \|
1618	pdUpTune_1to0_3 << 2 \|
1619	pdDnTune_1to0_3 << 0 );
1620	send_reg(125, reg_125);
1621	}
1622	void rfic :: set_reg_126(){
1623	int reg_126 = (
1624	cpUpTune_2to0_3 << 5 \|
1625	cpDnTune_2to0_3 << 2 \|
1626	pdEn_3 << 1 );
1627	send_reg(126, reg_126);
1628	}
1629	void rfic :: set_reg_127(){
1630	int reg_127 = (
1631	digClkPhase_7to0_3 << 0 );
1632	send_reg(127, reg_127);
1633	}
1634	void rfic :: set_reg_128(){
1635	int reg_128 = (
1636	Rst_n_async_3 << 7 );
1637	send_reg(128, reg_128);
1638	}
1639	void rfic :: read_reg_129(){
1640	int reg_129 = get_reg(129);
1641	L1_lup00_15to8_3 = reg_129;
1642	}
1643	void rfic :: read_reg_130(){
1644	int reg_130 = get_reg(130);
1645	L1_lup90_15to8_3 = reg_130;
1646	}
1647	void rfic :: read_reg_131(){
1648	int reg_131 = get_reg(131);
1649	Merg_ris_fin_3 = reg_131 >> 2;
1650	}
1651	void rfic :: read_reg_132(){
1652	int reg_132 = get_reg(132);
1653	Merg_fal_fin_3 = reg_132 >> 2;
1654	}
1655	void rfic :: set_reg_133(){
1656	int reg_133 = (
1657	Qg00degDelay_0to4_3 << 3 );
1658	send_reg(133, reg_133);
1659	}
1660	void rfic :: set_reg_134(){
1661	int reg_134 = (
1662	Qg90degDelay_0to4_3 << 3 );
1663	send_reg(134, reg_134);
1664	}
1665	void rfic :: set_reg_135(){
1666	int reg_135 = (
1667	Qg180degDelay_0to4_3 << 3 );
1668	send_reg(135, reg_135);
1669	}
1670	void rfic :: set_reg_136(){
1671	int reg_136 = (
1672	Qg270degDelay_0to4_3 << 3 );
1673	send_reg(136, reg_136);
1674	}
1675	void rfic :: set_reg_137(){
1676	int reg_137 = (
1677	DischargeTap16_0to3_3 << 4 \|
1678	ChargeTap16_0to3_3 << 0 );
1679	send_reg(137, reg_137);
1680	}
1681	void rfic :: set_reg_138(){
1682	int reg_138 = (
1683	DischargeTapn_0to3_3 << 4 \|
1684	ChargeTapn16_0to3_3 << 0 );
1685	send_reg(138, reg_138);
1686	}
1687	void rfic :: set_reg_139(){
1688	int reg_139 = (
1689	X1sel_32to39_3 << 0 );
1690	send_reg(139, reg_139);
1691	}
1692	void rfic :: set_reg_140(){
1693	int reg_140 = (
1694	X1sel_40to47_3 << 0 );
1695	send_reg(140, reg_140);
1696	}
1697	void rfic :: set_reg_141(){
1698	int reg_141 = (
1699	X2sel_32to36_3 << 3 );
1700	send_reg(141, reg_141);
1701	}
1702	void rfic :: set_reg_142(){
1703	int reg_142 = (
1704	X2sel_37to41_3 << 3 );
1705	send_reg(142, reg_142);
1706	}
1707	void rfic :: set_reg_143(){
1708	int reg_143 = (
1709	X4sel_32to36_3 << 3 );
1710	send_reg(143, reg_143);
1711	}
1712	void rfic :: set_reg_144(){
1713	int reg_144 = (
1714	X4sel_37to41_3 << 3 );
1715	send_reg(144, reg_144);
1716	}
1717	void rfic :: set_reg_145(){
1718	int reg_145 = (
1719	X8sel_32to36_3 << 3 );
1720	send_reg(145, reg_145);
1721	}
1722	void rfic :: set_reg_146(){
1723	int reg_146 = (
1724	X8sel_41_3 << 7 \|
1725	X8sel_37to40_3 << 3 );
1726	send_reg(146, reg_146);
1727	}
1728	void rfic :: set_reg_147(){
1729	int reg_147 = (
1730	qurx_180Cal_en << 7 \|
1731	qurx_0Cal_en << 6 );
1732	send_reg(147, reg_147);
1733	}
1734	void rfic :: set_reg_152(){
1735	int reg_152 = (
1736	extClkEn << 7 \|
1737	extClkEnBNOTD7 << 6 \|
1738	div2_rst << 5 \|
1739	TxChClkSel << 3 );
1740	send_reg(152, reg_152);
1741	}
1742	void rfic :: set_reg_153(){
1743	int reg_153 = (
1744	TxChClkEn << 5 );
1745	send_reg(153, reg_153);
1746	}
1747	void rfic :: set_reg_156(){
1748	int reg_156 = (
1749	tx_bb_en << 7 \|
1750	tx_bb_fdbk_bw << 5 \|
1751	tx_bb_fdbk_cal_en << 4 \|
1752	tx_bb_fdbk_cart_err_en << 3 \|
1753	tx_bb_fdbk_cart_fb_en << 2 \|
1754	tx_bb_fdbk_cart_fwd_en << 1 );
1755	send_reg(156, reg_156);
1756	}
1757	void rfic :: set_reg_157(){
1758	int reg_157 = (
1759	tx_bb_fdbk_en << 6 \|
1760	tx_bb_fdbk_1q_sel << 5 \|
1761	tx_bb_fdbk_lp << 2 );
1762	send_reg(157, reg_157);
1763	}
1764	void rfic :: set_reg_158(){
1765	int reg_158 = (
1766	tx_bb_fdbk_statt << 5 \|
1767	tx_bb_fdbk_swapi << 4 \|
1768	tx_bb_fdbk_swapq << 3 \|
1769	tx_bb_gain_cmp << 2 );
1770	send_reg(158, reg_158);
1771	}
1772	void rfic :: set_reg_159(){
1773	int reg_159 = (
1774	tx_bb_lp << 5 \|
1775	tx_bb_swapi << 4 \|
1776	tx_bb_swapq << 3 \|
1777	tx_butt_bw << 0 );
1778	send_reg(159, reg_159);
1779	}
1780	void rfic :: set_reg_160(){
1781	int reg_160 = (
1782	tx_bw_trck << 4 \|
1783	tx_cart_en << 3 );
1784	send_reg(160, reg_160);
1785	}
1786	void rfic :: set_reg_161(){
1787	int reg_161 = (
1788	tx_cart_fb_bb_statt << 3 );
1789	send_reg(161, reg_161);
1790	}
1791	void rfic :: set_reg_162(){
1792	int reg_162 = (
1793	tx_cart_fb_dcoc_dac_I1 << 2 );
1794	send_reg(162, reg_162);
1795	}
1796	void rfic :: set_reg_163(){
1797	int reg_163 = (
1798	tx_cart_fb_dcoc_dac_I2 << 2 );
1799	send_reg(163, reg_163);
1800	}
1801	void rfic :: set_reg_164(){
1802	int reg_164 = (
1803	tx_cart_fb_dcoc_dac_Q1 << 2 );
1804	send_reg(164, reg_164);
1805	}
1806	void rfic :: set_reg_165(){
1807	int reg_165 = (
1808	tx_cart_fb_dcoc_dac_Q2 << 2 );
1809	send_reg(165, reg_165);
1810	}
1811	void rfic :: set_reg_166(){
1812	int reg_166 = (
1813	CartesianFeedbackpathDCOCenable << 7 \|
1814	CartesianFeedbackpathenable << 6 \|
1815	CartesianFBpathHiResolutionDCOCenable << 5 \|
1816	CartesianFBpathBW << 1 );
1817	send_reg(166, reg_166);
1818	}
1819	void rfic :: set_reg_167(){
1820	int reg_167 = (
1821	CartesianFBRFGain << 2 );
1822	send_reg(167, reg_167);
1823	}
1824	void rfic :: set_reg_168(){
1825	int reg_168 = (
1826	CartesianFBpathSwapIandIx << 7 \|
1827	CartesianFBpathSwapQandQx << 6 \|
1828	CartesianFBpathSwitchtoforwardSummer << 5 \|
1829	tx_cart_fb_lo_select << 0 );
1830	send_reg(168, reg_168);
1831	}
1832	void rfic :: set_reg_169(){
1833	int reg_169 = (
1834	CartesianFBpathAmp1Gain << 6 \|
1835	CartesianFBpathAmp2Gain << 4 \|
1836	CartesianFBpathAmp3Gain << 2 \|
1837	CartesianFBpathAmp4Gain << 0 );
1838	send_reg(169, reg_169);
1839	}
1840	void rfic :: set_reg_170(){
1841	int reg_170 = (
1842	CartesianFBpathAmpCurrentSelect << 5 \|
1843	CartesianFBpathZeroEnable << 4 \|
1844	tx_cart_zero_statt << 0 );
1845	send_reg(170, reg_170);
1846	}
1847	void rfic :: set_reg_171(){
1848	int reg_171 = (
1849	tx_inbuf_bw << 6 \|
1850	tx_inbuf_statt << 3 );
1851	send_reg(171, reg_171);
1852	}
1853	void rfic :: set_reg_172(){
1854	int reg_172 = (
1855	tx_output_channel_sel << 5 );
1856	send_reg(172, reg_172);
1857	}
1858	void rfic :: set_reg_173(){
1859	int reg_173 = (
1860	tx_p1_bw << 4 \|
1861	tx_pw_bw1 << 2 );
1862	send_reg(173, reg_173);
1863	}
1864	void rfic :: set_reg_174(){
1865	int reg_174 = (
1866	tx_p2_bw2 << 4 \|
1867	PushPullBufferCurrent << 1 );
1868	send_reg(174, reg_174);
1869	}
1870	void rfic :: set_reg_175(){
1871	int reg_175 = (
1872	tx_rf_aoc_bw << 6 \|
1873	RFForwardPathEnable_toMUX << 5 \|
1874	RFForwardPathEnable_ExternalPinenable << 4 \|
1875	tx_rf_fwd_lp << 1 );
1876	send_reg(175, reg_175);
1877	}
1878	void rfic :: set_reg_176(){
1879	int reg_176 = (
1880	tx_rf_fwd_statt1 << 5 \|
1881	tx_rf_fwd_statt2 << 2 );
1882	send_reg(176, reg_176);
1883	}
1884	void rfic :: set_reg_177(){
1885	int reg_177 = (
1886	BBQDivideby2or4Select << 7 \|
1887	BBQQuadGenEnable << 6 \|
1888	BBQPolyphaseQuadGenEnable << 5 );
1889	send_reg(177, reg_177);
1890	}
1891	void rfic :: set_reg_178(){
1892	int reg_178 = (
1893	lofb_tun_s << 4 \|
1894	lofb_tun_sx << 0 );
1895	send_reg(178, reg_178);
1896	}
1897	void rfic :: set_reg_179(){
1898	int reg_179 = (
1899	lofw_tun_s2 << 4 \|
1900	lofw_tun_sx2 << 0 );
1901	send_reg(179, reg_179);
1902	}
1903	void rfic :: set_reg_180(){
1904	int reg_180 = (
1905	reserve_tx26 << 0 );
1906	send_reg(180, reg_180);
1907	}
1908	void rfic :: set_reg_181(){
1909	int reg_181 = (
1910	reserve_tx27 << 0 );
1911	send_reg(181, reg_181);
1912	}
1913	void rfic :: set_reg_192(){
1914	int reg_192 = (
1915	rx_Idac << 3 \|
1916	rx_dcs << 1 \|
1917	rx_den << 0 );
1918	send_reg(192, reg_192);
1919	}
1920	void rfic :: set_reg_193(){
1921	int reg_193 = (
1922	rx_Qdac << 3 \|
1923	rx_cmpen << 1 \|
1924	rx_dcoc << 0 );
1925	send_reg(193, reg_193);
1926	}
1927	void rfic :: set_reg_194(){
1928	int reg_194 = (
1929	rx_ten << 7 \|
1930	rx_ren << 6 \|
1931	rx_dven << 4 \|
1932	rx_dv << 0 );
1933	send_reg(194, reg_194);
1934	}
1935	void rfic :: set_reg_195(){
1936	int reg_195 = (
1937	rx_extc << 7 \|
1938	rx_cen << 4 \|
1939	rx_chck << 2 \|
1940	rx_chcken << 1 \|
1941	rx_fen << 0 );
1942	send_reg(195, reg_195);
1943	}
1944	void rfic :: set_reg_196(){
1945	int reg_196 = (
1946	rx_onchen << 7 \|
1947	rx_offchen << 6 \|
1948	rx_foe << 0 );
1949	send_reg(196, reg_196);
1950	}
1951	void rfic :: set_reg_197(){
1952	int reg_197 = (
1953	rx_offch << 5 \|
1954	rx_onchf << 3 \|
1955	rx_onchc << 1 );
1956	send_reg(197, reg_197);
1957	}
1958	void rfic :: set_reg_198(){
1959	int reg_198 = (
1960	rx_qs << 5 \|
1961	rx_bqg << 3 \|
1962	rx_rq << 0 );
1963	send_reg(198, reg_198);
1964	}
1965	void rfic :: set_reg_199(){
1966	int reg_199 = (
1967	rx_rv << 5 \|
1968	rx_rip << 2 \|
1969	rx_rfp << 0 );
1970	send_reg(199, reg_199);
1971	}
1972	void rfic :: set_reg_200(){
1973	int reg_200 = (
1974	rx_cp_12to8 << 3 \|
1975	rx_gs << 0 );
1976	send_reg(200, reg_200);
1977	}
1978	void rfic :: set_reg_201(){
1979	int reg_201 = (
1980	rx_cp_7to0 << 0 );
1981	send_reg(201, reg_201);
1982	}
1983	void rfic :: set_reg_202(){
1984	int reg_202 = (
1985	rx_cv_10to3 << 0 );
1986	send_reg(202, reg_202);
1987	}
1988	void rfic :: set_reg_203(){
1989	int reg_203 = (
1990	rx_cv_2to0 << 5 \|
1991	rx_cc_2to0 << 2 \|
1992	rx_cq_9to8 << 0 );
1993	send_reg(203, reg_203);
1994	}
1995	void rfic :: set_reg_204(){
1996	int reg_204 = (
1997	rx_cq_7to0 << 0 );
1998	send_reg(204, reg_204);
1999	}
2000
2001
2002	void rfic :: set_reg_206(){
2003	int reg_206 = (
2004	poly_en << 7 );
2005	send_reg(206, reg_206);
2006	}
2007	void rfic :: set_reg_207(){
2008	int reg_207 = (
2009	lorx_tun_s << 4 \|
2010	lorx_tun_sx << 0 );
2011	send_reg(207, reg_207);
2012	}
2013	void rfic :: read_reg_208(){
2014	int reg_208 = get_reg(208);
2015	rx_Icmpo = reg_208 >> 5;
2016	rx_Iodac = reg_208 % 64;
2017	}
2018	void rfic :: read_reg_209(){
2019	int reg_209 = get_reg(209);
2020	rx_Qcmpo = reg_209 >> 5;
2021	rx_Qodac = reg_209 % 64;
2022	}
2023	void rfic :: read_reg_210(){
2024	int reg_210 = get_reg(210);
2025	rx_rc = reg_210;
2026	}
2027	void rfic :: set_reg_220(){
2028	int reg_220 = (
2029	shft_cml_in << 7 \|
2030	vagenable1 << 6 \|
2031	vagenable2 << 5 );
2032	send_reg(220, reg_220);
2033	}
2034	void rfic :: set_reg_222(){
2035	int reg_222 = (
2036	TestMuxBufferEnable << 7 \|
2037	TestMuxEnable << 6 \|
2038	TestMuxSetting << 0 );
2039	send_reg(222, reg_222);
2040	}
2041
2042
2043	bool rfic :: set_rx_gain(float gain){
2044	// Set RX gain
2045	// @param gain){ gain in dB
2046	// Four parameters){ rx_bqg, rx_dcs, rx_gs, rx_rip
2047	// 1 to 39 dB of gain (0 to 38){
2048	// Not all steps available
2049	if (gain < 0.0) gain = 0.0;
2050	if (gain > 38.0)gain = 38.0;
2051
2052	if (gain <= 3){
2053	rx_bqg = 3; //reg 198
2054	rx_dcs = 0; //reg 192
2055	rx_gs = 4; //reg 200
2056	rx_rip = 4; //reg 199
2057	}
2058	else if ( gain >= 3 && gain < 4){
2059	rx_bqg = 3;
2060	rx_dcs = 0;
2061	rx_gs = 4;
2062	rx_rip = 3;
2063	}
2064	else if ( gain >= 4 && gain < 5){
2065	rx_bqg = 3;
2066	rx_dcs = 0;
2067	rx_gs = 2;
2068	rx_rip = 4;
2069	}
2070	else if ( gain >=5 && gain < 6){
2071	rx_bqg = 3;
2072	rx_dcs = 0;
2073	rx_gs = 3;
2074	rx_rip = 3;
2075	}
2076	else if ( gain >= 6 && gain < 7){
2077	rx_bqg = 3;
2078	rx_dcs = 0;
2079	rx_gs = 4;
2080	rx_rip = 2;
2081	}
2082	else if ( gain >= 7 && gain < 8){
2083	rx_bqg = 3;
2084	rx_dcs = 0;
2085	rx_gs = 2;
2086	rx_rip = 3;
2087	}
2088	else if ( gain >= 8 && gain < 9){
2089	rx_bqg = 3;
2090	rx_dcs = 0;
2091	rx_gs = 3;
2092	rx_rip = 2;
2093	}
2094	else if ( gain >= 9 && gain < 10){
2095	rx_bqg = 3;
2096	rx_dcs = 0;
2097	rx_gs = 1;
2098	rx_rip = 3;
2099	}
2100	else if ( gain >= 10 && gain < 11){
2101	rx_bqg = 3;
2102	rx_dcs = 0;
2103	rx_gs = 2;
2104	rx_rip = 2;
2105	}
2106	else if ( gain >= 11 && gain < 12){
2107	rx_bqg = 3;
2108	rx_dcs = 0;
2109	rx_gs = 0;
2110	rx_rip = 3;
2111	}
2112	else if ( gain >= 12 && gain < 13){
2113	rx_bqg = 2;
2114	rx_dcs = 0;
2115	rx_gs = 4;
2116	rx_rip = 2;
2117	}
2118	else if ( gain >= 13 && gain < 14){
2119	rx_bqg = 3;
2120	rx_dcs = 0;
2121	rx_gs = 2;
2122	rx_rip = 1;
2123	}
2124	else if ( gain >= 14 && gain < 15){
2125	rx_bqg = 3;
2126	rx_dcs = 0;
2127	rx_gs = 0;
2128	rx_rip = 2;
2129	}
2130	else if ( gain >= 15 && gain < 16){
2131	rx_bqg = 2;
2132	rx_dcs = 0;
2133	rx_gs = 1;
2134	rx_rip = 3;
2135	}
2136	else if ( gain >= 16 && gain < 17){
2137	rx_bqg = 2;
2138	rx_dcs = 0;
2139	rx_gs = 2;
2140	rx_rip = 2;
2141	}
2142	else if ( gain >= 17 && gain < 18){
2143	rx_bqg = 3;
2144	rx_dcs = 0;
2145	rx_gs = 0;
2146	rx_rip = 2;
2147	}
2148	else if ( gain >= 18 && gain < 19){
2149	rx_bqg = 3;
2150	rx_dcs = 0;
2151	rx_gs = 1;
2152	rx_rip = 0;
2153	}
2154	else if ( gain >= 19 && gain < 20){
2155	rx_bqg = 2;
2156	rx_dcs = 0;
2157	rx_gs = 2;
2158	rx_rip = 1;
2159	}
2160	else if ( gain >= 20 && gain < 21){
2161	rx_bqg = 3;
2162	rx_dcs = 0;
2163	rx_gs = 0;
2164	rx_rip = 0;
2165	}
2166	else if ( gain >= 21 && gain < 22){
2167	rx_bqg = 2;
2168	rx_dcs = 0;
2169	rx_gs = 1;
2170	rx_rip = 1;
2171	}
2172	else if ( gain >= 22 && gain < 23){
2173	rx_bqg = 1;
2174	rx_dcs = 1;
2175	rx_gs = 2;
2176	rx_rip = 2;
2177	}
2178	else if ( gain >= 23 && gain < 24){
2179	rx_bqg = 2;
2180	rx_dcs = 0;
2181	rx_gs = 0;
2182	rx_rip = 1;
2183	}
2184	else if ( gain >= 24 && gain < 25){
2185	rx_bqg = 1;
2186	rx_dcs = 1;
2187	rx_gs = 1;
2188	rx_rip = 2;
2189	}
2190	else if ( gain >= 25 && gain < 26){
2191	rx_bqg = 1;
2192	rx_dcs = 1;
2193	rx_gs = 2;
2194	rx_rip = 1;
2195	}
2196	else if ( gain >= 26 && gain < 27){
2197	rx_bqg = 1;
2198	rx_dcs = 1;
2199	rx_gs = 3;
2200	rx_rip = 0;
2201	}
2202	else if ( gain >= 27 && gain < 28){
2203	rx_bqg = 1;
2204	rx_dcs = 1;
2205	rx_gs = 1;
2206	rx_rip = 1;
2207	}
2208	else if ( gain >= 28 && gain < 29){
2209	rx_bqg = 1;
2210	rx_dcs = 1;
2211	rx_gs = 2;
2212	rx_rip = 0;
2213	}
2214	else if ( gain >= 29 && gain < 30){
2215	rx_bqg = 1;
2216	rx_dcs = 1;
2217	rx_gs = 0;
2218	rx_rip = 1;
2219	}
2220	else if ( gain >= 30 && gain < 31){
2221	rx_bqg = 1;
2222	rx_dcs = 1;
2223	rx_gs = 1;
2224	rx_rip = 0;
2225	}
2226	else if ( gain >= 31 && gain < 32){
2227	rx_bqg = 0;
2228	rx_dcs = 3;
2229	rx_gs = 2;
2230	rx_rip = 1;
2231	}
2232	else if ( gain >= 32 && gain < 33){
2233	rx_bqg = 1;
2234	rx_dcs = 1;
2235	rx_gs = 0;
2236	rx_rip = 0;
2237	}
2238	else if ( gain >= 33 && gain < 34){
2239	rx_bqg = 0;
2240	rx_dcs = 3;
2241	rx_gs = 1;
2242	rx_rip = 1;
2243	}
2244	else if ( gain >= 34 && gain < 35){
2245	rx_bqg = 0;
2246	rx_dcs = 3;
2247	rx_gs = 2;
2248	rx_rip = 0;
2249	}
2250	else if ( gain >= 35 && gain < 36){
2251	rx_bqg = 0;
2252	rx_dcs = 3;
2253	rx_gs = 0;
2254	rx_rip = 1;
2255	}
2256	else if ( gain >= 36 && gain < 38){
2257	rx_bqg = 0;
2258	rx_dcs = 3;
2259	rx_gs = 1;
2260	rx_rip = 0;
2261	}
2262	else if ( gain >= 38){
2263	rx_bqg = 0;
2264	rx_dcs = 3;
2265	rx_gs = 0;
2266	rx_rip = 0;
2267	}
2268	set_reg_198();
2269	set_reg_192();
2270	set_reg_200();
2271	set_reg_199();
2272	return true; //this function always returns true. Maximum gain is 38
2273	}
2274
2275	bool rfic :: set_tx_gain(float gain){
2276	// Set TX gain
2277	// @param gain){ output gain in dB
2278	// Two parameters){
2279	// tx_rf_fwd_statt1, tx_rf_fwd_statt2
2280	// (45 dB of range)
2281	// 5 dB steps
2282	if (gain < 0.0) gain = 0.0;
2283	if (gain > 45.0) gain = 45.0;
2284
2285	if (gain <= 2.5){
2286	tx_rf_fwd_statt1 = 7;
2287	tx_rf_fwd_statt2 = 7;
2288	}
2289	else if ( gain > 2.5 && gain <= 7.5){
2290	tx_rf_fwd_statt1 = 3;
2291	tx_rf_fwd_statt2 = 7;
2292	}
2293	else if ( gain > 7.5 && gain <= 12.5){
2294	tx_rf_fwd_statt1 = 1;
2295	tx_rf_fwd_statt2 = 7;
2296	}
2297	else if ( gain > 12.5 && gain <= 17.5){
2298	tx_rf_fwd_statt1 = 3;
2299	tx_rf_fwd_statt2 = 3;
2300	}
2301	else if ( gain > 17.5 && gain <= 22.5){
2302	tx_rf_fwd_statt1 = 1;
2303	tx_rf_fwd_statt2 = 3;
2304	}
2305	else if ( gain > 22.5 && gain <= 27.5){
2306	tx_rf_fwd_statt1 = 0;
2307	tx_rf_fwd_statt2 = 3;
2308	}
2309	else if ( gain > 27.5 && gain <= 32.5){
2310	tx_rf_fwd_statt1 = 1;
2311	tx_rf_fwd_statt2 = 1;
2312	}
2313	else if ( gain > 32.5 && gain <= 37.5){
2314	tx_rf_fwd_statt1 = 0;
2315	tx_rf_fwd_statt2 = 1;
2316	}
2317	else if ( gain > 37.5 && gain <= 42.5){
2318	tx_rf_fwd_statt1 = 1;
2319	tx_rf_fwd_statt2 = 0;
2320	}
2321	else if ( gain > 42.5){
2322	tx_rf_fwd_statt1 = 0;
2323	tx_rf_fwd_statt2 = 0;
2324	}
2325	set_reg_176();
2326	return true; //this function always returns true. Maximum gain is 45
2327	}
2328	void rfic ::set_fb_gain(float gain){
2329	// Set Feedback path gain
2330	// @param gain){ output gain in dB
2331	// parameters){
2332	// CartesianFBpathAmp1Gain, CartesianFBpathAmp2Gain,
2333	// CartesianFBpathAmp3Gain, CartesianFBpathAmp4Gain
2334	// (40 dB of range)
2335	// 5 dB steps
2336	// FIXME
2337	if (gain < 0.0)gain = 0.0;
2338	if (gain > 40.0) gain = 40.0;
2339
2340	if (gain <= 2.5){
2341	CartesianFBpathAmp1Gain = 3;
2342	CartesianFBpathAmp2Gain = 3;
2343	CartesianFBpathAmp3Gain = 3;
2344	CartesianFBpathAmp4Gain = 3;
2345	}
2346	else if ( gain > 2.5 && gain <= 7.5){
2347	CartesianFBpathAmp1Gain = 3;
2348	CartesianFBpathAmp2Gain = 3;
2349	CartesianFBpathAmp3Gain = 3;
2350	CartesianFBpathAmp4Gain = 1;
2351	}
2352	else if ( gain > 7.5 && gain <= 12.5){
2353	CartesianFBpathAmp1Gain = 3;
2354	CartesianFBpathAmp2Gain = 3;
2355	CartesianFBpathAmp3Gain = 1;
2356	CartesianFBpathAmp4Gain = 1;
2357	}
2358	else if ( gain > 12.5 && gain <= 17.5){
2359	CartesianFBpathAmp1Gain = 3;
2360	CartesianFBpathAmp2Gain = 1;
2361	CartesianFBpathAmp3Gain = 1;
2362	CartesianFBpathAmp4Gain = 1;
2363	}
2364	else if ( gain > 17.5 && gain <= 22.5){
2365	CartesianFBpathAmp1Gain = 1;
2366	CartesianFBpathAmp2Gain = 1;
2367	CartesianFBpathAmp3Gain = 1;
2368	CartesianFBpathAmp4Gain = 1;
2369	}
2370	else if ( gain > 22.5 && gain <= 27.5){
2371	CartesianFBpathAmp1Gain = 1;
2372	CartesianFBpathAmp2Gain = 1;
2373	CartesianFBpathAmp3Gain = 1;
2374	CartesianFBpathAmp4Gain = 0;
2375	}
2376	else if ( gain > 27.5 && gain <= 32.5){
2377	CartesianFBpathAmp1Gain = 1;
2378	CartesianFBpathAmp2Gain = 1;
2379	CartesianFBpathAmp3Gain = 0;
2380	CartesianFBpathAmp4Gain = 0;
2381	}
2382	else if ( gain > 32.5 && gain <= 37.5){
2383	CartesianFBpathAmp1Gain = 1;
2384	CartesianFBpathAmp2Gain = 0;
2385	CartesianFBpathAmp3Gain = 0;
2386	CartesianFBpathAmp4Gain = 0;
2387	}
2388	else if ( gain > 37.5){
2389	CartesianFBpathAmp1Gain = 0;
2390	CartesianFBpathAmp2Gain = 0;
2391	CartesianFBpathAmp3Gain = 0;
2392	CartesianFBpathAmp4Gain = 0;
2393	}
2394	set_reg_169();
2395	}
2396
2397	void rfic :: calc_freq_vars(double _Fclk,double _Fout,int ret_arr[]){
2398	//
2399	//@param Fclk: Clock frequency of board (Hz)
2400	//@type Fclk: float
2401	//@param Fout: Desired clock frequency for one of three frequency synthesizers (Hz)
2402	//@type Fout: float
2403	//
2404	// Calculate RFIC register variables to set frequency of frequency synthesizers
2405	// data1 corresponds to Ngt, D7, a single bit
2406	// data2 corresponds to NorNdiv4, D6-D0, up to seven bits
2407	// data3 corresponds to RorFrNpRdiv4, up to 26 bits
2408	// D7-D0, D7-D0, D7-D0, D7-D6
2409	// Returns Ngt, NorNdiv4, RorFrNpRdiv4_25to18, RorFrNpRdiv4_17to10,
2410	// RorFrNpRdiv4_9to2, RorFrNpRdiv4_1to0
2411	float NpR;
2412	int data1,data2,data3,temp,Ngt;
2413	//int ret_arr[6];
2414	if (_Fout > _Fclk / 4){
2415	NpR = pow(2,-26) * floor(pow(2,26) * _Fclk / _Fout);
2416	data1 = 0;
2417	data2 = int(floor(NpR));
2418	data3 = int(pow(2,26) * (NpR - floor(NpR)));
2419	}
2420	else{
2421	NpR = pow(2,-24)* int(pow(2,24) * _Fclk / _Fout);
2422	data1 = 1;
2423	data2 = int(floor(NpR / 4));
2424	data3 = int(pow(2,26) * (NpR / 4 - floor(NpR / 4)));
2425	}
2426
2427	Ngt = data1;
2428
2429	ret_arr[0]= Ngt;
2430	NorNdiv4 = data2;
2431	ret_arr[1]=NorNdiv4;
2432
2433	RorFrNpRdiv4_25to18 = data3 >> 18;
2434	ret_arr[2]=RorFrNpRdiv4_25to18;
2435	temp = data3 % int(pow(2,18));
2436	RorFrNpRdiv4_17to10 = temp >> 10;
2437	ret_arr[3]= RorFrNpRdiv4_17to10;
2438	temp = data3 % int(pow(2,10));
2439	RorFrNpRdiv4_9to2 = temp >> 2;
2440	ret_arr[4]= RorFrNpRdiv4_9to2;
2441	RorFrNpRdiv4_1to0 = data3 % int(pow(2,2));
2442	ret_arr[5]=RorFrNpRdiv4_1to0;
2443
2444	}
2445
2446	void rfic :: calc_phase_vars(double _Fclk, double _Fout,double phsh,int ret_arr[]){
2447	//
2448	//@param _Fclk: Clock frequency of board (Hz)
2449	//@type _Fclk: float
2450	//@param _Fout: Desired clock frequency for one of three frequency synthesizers (Hz)
2451	//@type _Fout: float
2452	//@param phsh: Desired phase shift in degrees
2453	//@type phsh: float
2454	//
2455	// Calculate RFIC register variables to set phase of frequency synthesizers
2456	// data1 is NGT3_phsh, D7, a single bit
2457	// data2 is NorNdiv4_phsh, D6-D0, up to 7 bits
2458	// data3 is RorFrNpRdiv4_phsh, up to 26 bits
2459	// D7-D0, D7-D0, D7-D0, D7-D6
2460	// Returns Ngt_phsh, NorNdiv4_phsh, RorFrNpRdiv4_25to18_phsh,
2461	// RorFrNpRdiv4_17to10_phsh, RorFrNpRdiv4_9to2_phsh, RorFrNpRdiv4_1to0_phsh
2462
2463	float mod1,tmp,NpR,NpR_ph;
2464	int data1,data2,data3,temp,Ngt_phsh,RorFrNpRdiv4_17to10_phsh,RorFrNpRdiv4_9to2_phsh,RorFrNpRdiv4_25to18_phsh,RorFrNpRdiv4_1to0_phsh;
2465
2466	if (_Fout <= _Fclk / 4){
2467	mod1 = phsh - 360 * floor(phsh / 360);
2468	NpR = pow(2,-24) * int(pow(2,24) * _Fclk / _Fout);
2469	tmp = (1 + mod1 / 360 / 2) * NpR;
2470	}
2471	else{
2472	mod1 = phsh - 360 * floor(phsh / 360);
2473	NpR = pow(2,-26) * int(pow(2,26) * _Fclk / _Fout);
2474	tmp = (1 + mod1 / 360 / 2) * NpR;
2475	}
2476	if (tmp < 4){
2477	NpR_ph = pow(2,-26) * int(pow(2,26) * (1 + mod1 / 360 / 8) * NpR);
2478	data1 = 0;
2479	data2 = int(floor(NpR_ph));
2480	data3 = int(pow(2,26) * (NpR_ph - floor(NpR_ph)));
2481	}
2482	else if ((tmp >=4) && (tmp < 508)){
2483	NpR_ph = pow(2,-24) * int(pow(2,24) * tmp);
2484	data1 = 1;
2485	data2 = int(floor(NpR_ph / 4));
2486	data3 = int(pow(2,26) * (NpR_ph / 4 - floor(NpR_ph / 4)));
2487	}
2488	else if (tmp >= 508){
2489	NpR_ph = pow(2,-24) * int(pow(2,24) * (1 + (mod1 - 360) / 360 /2) * NpR);
2490	data1 = 1;
2491	data2 = int(floor(NpR_ph / 4));
2492	data3 = int(pow(2,26) * (NpR_ph / 4 - floor(NpR_ph / 4)));
2493	}
2494	Ngt_phsh = data1;
2495	ret_arr[0]=Ngt_phsh;
2496
2497	NorNdiv4_phsh = data2;
2498	ret_arr[1]=NorNdiv4_phsh;
2499	RorFrNpRdiv4_25to18_phsh = data3 >> 18;
2500	ret_arr[2]=RorFrNpRdiv4_25to18_phsh;
2501	temp = data3 % int(pow(2,18));
2502	RorFrNpRdiv4_17to10_phsh = temp >> 10;
2503	ret_arr[3]=RorFrNpRdiv4_17to10_phsh;
2504	temp = data3 % int(pow(2,20));
2505	RorFrNpRdiv4_9to2_phsh = temp >> 2;
2506	ret_arr[4]=RorFrNpRdiv4_9to2_phsh;
2507	RorFrNpRdiv4_1to0_phsh = data3 % 4;
2508	ret_arr[5]=RorFrNpRdiv4_1to0_phsh;
2509
2510	}
2511
2512
2513	struct freq_result_t rfic :: set_rx_freq(double target_freq){
2514	//
2515	//@param target_freq: desired receiver frequency in Hz
2516	//@returns (ok, actual_baseb&&_freq) where:
2517	// ok is True or False && indicates success or failure,
2518	// actual_baseb&&_freq is the RF frequency that corresponds to DC in the IF.
2519	//
2520
2521	// Go through Quadrature Generation Initialization Sequence
2522	struct freq_result_t args = {false, 0};
2523	//target_freq = target_freq + 4000000
2524	float try_freq;
2525	if (target_freq <= 500000000){
2526	// Below 500 MHz
2527	std::cout << "Below 500 MHz, divide by 2"<<std::endl;
2528	// Use QuIET frequency divided by 2
2529	// Step 1
2530	X1sel_32to39_3 = 0;
2531	X1sel_40to47_3 = 62;
2532	X2sel_32to36_3 = 0;
2533	X2sel_37to41_3 = 0;
2534	X4sel_32to36_3 = 0;
2535	X4sel_37to41_3 = 0;
2536
2537	set_reg_139();
2538	set_reg_140();
2539	set_reg_141();
2540	set_reg_142();
2541	set_reg_143();
2542	set_reg_144();
2543
2544	// Step 2
2545	X1sel_40to47_3 = 63;
2546
2547	set_reg_140();
2548
2549	try_freq = target_freq * 2;
2550
2551	}
2552	else if ((target_freq > 500000000) && (target_freq <= 1000000000)){
2553	// Between 500 MHz && 1 GHz
2554	std::cout << "Between 500 MHz and 1 GHz"<<std::endl;
2555	// Use QuIET frequency
2556	// Step 1
2557	X1sel_32to39_3 = 1;
2558	X1sel_40to47_3 = 192;
2559	X2sel_32to36_3 = 0;
2560	X2sel_37to41_3 = 0;
2561	X4sel_32to36_3 = 0;
2562	X4sel_37to41_3 = 0;
2563
2564	set_reg_139();
2565	set_reg_140();
2566	set_reg_141();
2567	set_reg_142();
2568	set_reg_143();
2569	set_reg_144();
2570
2571	// Step 2
2572	X1sel_32to39_3 = 73;
2573
2574	set_reg_139();
2575
2576	// Step 3
2577	X1sel_32to39_3 = 201;
2578
2579	set_reg_139();
2580
2581	try_freq = target_freq;
2582
2583	// Set Quadrature Generator Charge/Discharge Taps
2584	DischargeTap16_0to3_3 = 6;
2585	ChargeTap16_0to3_3 = 7;
2586	DischargeTapn_0to3_3 = 0;
2587	ChargeTapn16_0to3_3 = 5;
2588
2589	// Set Quadrature Generator Delays
2590	Qg00degDelay_0to4_3 = 16;
2591	Qg90degDelay_0to4_3 = 31;
2592	Qg180degDelay_0to4_3 = 0;
2593	Qg270degDelay_0to4_3 = 31;
2594
2595	set_reg_133();
2596	set_reg_134();
2597	set_reg_135();
2598	set_reg_136();
2599	set_reg_137();
2600	set_reg_138();
2601	}
2602
2603	else if ((target_freq > 1000000000) && (target_freq <= 2000000000)){
2604	// Between 1 GHz && 2 GHz
2605	std::cout << "Between 1 GHz and 2 GHz, multiply by 2"<< std::endl;
2606	// Use QuIET multiplied by 2
2607	// Step 1
2608	X1sel_32to39_3 = 0;
2609	X1sel_40to47_3 = 0;
2610	X2sel_32to36_3 = 0;
2611	X2sel_37to41_3 = 7;
2612	X4sel_32to36_3 = 0;
2613	X4sel_37to41_3 = 0;
2614
2615	set_reg_139();
2616	set_reg_140();
2617	set_reg_141();
2618	set_reg_142();
2619	set_reg_143();
2620	set_reg_144();
2621
2622	// Step 2
2623	X2sel_32to36_3 = 9;
2624
2625	set_reg_141();
2626
2627	// Step 3
2628	X2sel_32to36_3 = 25;
2629
2630	set_reg_141();
2631
2632	// Step 4
2633	X2sel_32to36_3 = 16;
2634
2635	set_reg_141();
2636
2637	try_freq = target_freq / 2;
2638
2639	// Set Quadrature Generator Charge/Discharge Taps
2640	DischargeTap16_0to3_3 = 9;
2641	ChargeTap16_0to3_3 = 3;
2642	DischargeTapn_0to3_3 = 3;
2643	ChargeTapn16_0to3_3 = 5;
2644
2645	// Set Quadrature Generator Delays
2646	Qg00degDelay_0to4_3 = 31;
2647	Qg90degDelay_0to4_3 = 31;
2648	Qg180degDelay_0to4_3 = 0;
2649	Qg270degDelay_0to4_3 = 31;
2650
2651	set_reg_133();
2652	set_reg_134();
2653	set_reg_135();
2654	set_reg_136();
2655	set_reg_137();
2656	set_reg_138();
2657	}
2658
2659	else if ((target_freq > 2000000000.0) && (target_freq <= 4000000000.0)){
2660	// 2 to 4 GHz
2661	std::cout<< "From 2 to 4 GHz, multiply by 4"<<std::endl;
2662	// Use QuIET frequency multiplied by 4
2663	// Step 1
2664	X1sel_32to39_3 = 0;
2665	X1sel_40to47_3 = 0;
2666	X2sel_32to36_3 = 0;
2667	X2sel_37to41_3 = 0;
2668	X4sel_32to36_3 = 0;
2669	X4sel_37to41_3 = 7;
2670
2671	set_reg_139();
2672	set_reg_140();
2673	set_reg_141();
2674	set_reg_142();
2675	set_reg_143();
2676	set_reg_144();
2677
2678	// Step 2
2679	X4sel_32to36_3 = 9;
2680
2681	set_reg_143();
2682
2683	// Step 3
2684	X4sel_32to36_3 = 25;
2685
2686	set_reg_143();
2687
2688	try_freq = target_freq / 4;
2689
2690	// Set Quadrature Generator Charge/Discharge Taps
2691	DischargeTap16_0to3_3 = 16;
2692	ChargeTap16_0to3_3 = 0;
2693	DischargeTapn_0to3_3 = 7;
2694	ChargeTapn16_0to3_3 = 7;
2695
2696	// Set Quadrature Generator Delays
2697	Qg00degDelay_0to4_3 = 0;
2698	Qg90degDelay_0to4_3 = 31;
2699	Qg180degDelay_0to4_3 = 0;
2700	Qg270degDelay_0to4_3 = 31;
2701
2702	set_reg_133();
2703	set_reg_134();
2704	set_reg_135();
2705	set_reg_136();
2706	set_reg_137();
2707	set_reg_138();
2708	}
2709
2710	else if (target_freq > 4000000000.0){
2711	// Above 4 GHz, doesn't work
2712	args.ok = false;
2713	args.baseband_freq = target_freq;
2714	return args;
2715	}
2716	// FIXME
2717	/*// Above 4 GHz
2718	std::cout<< "Above 4 GHz, multiply by 8"<<std::endl;
2719	// Use QuIET frequency multiplied by 8
2720	// Step 1
2721	X1sel_32to39_3 = 0;
2722	X1sel_40to47_3 = 0;
2723	X2sel_32to36_3 = 0;
2724	X2sel_37to41_3 = 0;
2725	X4sel_32to36_3 = 0;
2726	X4sel_37to41_3 = 0;
2727	X8sel_32to36_3 = 0;
2728	X8sel_41_3 = 0;
2729	X8sel_37to40_3 = 7;
2730
2731	set_reg_139();
2732	set_reg_140();
2733	set_reg_141();
2734	set_reg_142();
2735	set_reg_143();
2736	set_reg_144();
2737	set_reg_145();
2738	set_reg_146();
2739
2740	// Step 2
2741	X8sel_32to36_3 = 9;
2742
2743	set_reg_145();
2744
2745	// Step 3
2746	X8sel_32to36_3 = 25;
2747
2748	set_reg_145();
2749
2750	try_freq = target_freq / 8;
2751
2752	// Set Quadrature Generator Charge/Discharge Taps
2753	ChargeTap16_0to3_3 = 15;
2754	ChargeTapn16_0to3_3 = 15;
2755
2756	DischargeTap16_0to3_3 = 6;
2757	DischargeTapn16_0to3_3 = 4;
2758
2759	set_reg_137();
2760	set_reg_138();*/
2761
2762
2763	Foutrx = target_freq;
2764	int ret_arr[6];
2765	calc_freq_vars(Fclk, try_freq,ret_arr);
2766	Ngt3_3 = ret_arr[0];
2767	NorNdiv4_3= ret_arr[1];
2768	RorFrNpRdiv4_25to18_3= ret_arr[2];
2769	RorFrNpRdiv4_17to10_3= ret_arr[3];
2770	RorFrNpRdiv4_9to2_3= ret_arr[4];
2771	RorFrNpRdiv4_1to0_3= ret_arr[5];
2772
2773
2774	set_reg_104();
2775	set_reg_105();
2776	set_reg_106();
2777	set_reg_107();
2778	set_reg_108();
2779
2780	args.ok = true;
2781	args.baseband_freq = target_freq;
2782	return args;
2783	//FIXME -- How do I know if the RFIC successfully attained the desired frequency?//
2784
2785	}
2786
2787	struct freq_result_t rfic :: set_tx_freq(double target_freq){
2788	//
2789	//@param target_freq: desired transmitter frequency in Hz
2790	//@returns (ok, actual_baseb&&_freq) where:
2791	// ok is True or False && indicates success or failure,
2792	// actual_baseb&&_freq is the RF frequency that corresponds to DC in the IF.
2793	//
2794
2795	// Go through Quadrature Generation Initialization Sequence
2796
2797	// FIXME
2798	//target_freq = target_freq + 4000000
2799	//target_freq = target_freq + 1000000
2800
2801	struct freq_result_t args = {false, 0};
2802
2803	double try_freq;
2804	if (target_freq <= 500000000.0){
2805	std::cout<< "Below 500 MHz, divide by 2"<<std::endl;
2806	// Use QuIET frequency divided by 2
2807	// Step 1
2808	X1sel_32to39 = 0;
2809	X1sel_40to47 = 62;
2810	X2sel_32to36 = 0;
2811	X2sel_37to41 = 0;
2812	X4sel_32to36 = 0;
2813	X4sel_37to41 = 0;
2814
2815	set_reg_35();
2816	set_reg_36();
2817	set_reg_37();
2818	set_reg_38();
2819	set_reg_39();
2820	set_reg_40();
2821
2822	// Step 2
2823	X1sel_40to47 = 63;
2824
2825	set_reg_36();
2826
2827	try_freq = target_freq * 2;
2828	}
2829	else if ((target_freq > 500000000.0) && (target_freq <= 1000000000.0)){
2830	std::cout<< "Between 500 MHz and 1 GHz"<<std::endl;
2831	// Use QuIET frequency
2832	// Step 1
2833	X1sel_32to39 = 1;
2834	X1sel_40to47 = 192;
2835	X2sel_32to36 = 0;
2836	X2sel_37to41 = 0;
2837	X4sel_32to36 = 0;
2838	X4sel_37to41 = 0;
2839
2840	set_reg_35();
2841	set_reg_36();
2842	set_reg_37();
2843	set_reg_38();
2844	set_reg_39();
2845	set_reg_40();
2846
2847	// Step 2
2848	X1sel_32to39 = 73;
2849
2850	set_reg_35();
2851
2852	// Step 3
2853	X1sel_32to39 = 201;
2854
2855	set_reg_35();
2856
2857	try_freq = target_freq;
2858
2859	// Set Quadrature Generator Charge/Discharge Taps && Delays
2860	Qg00degDelay_0to4 = 15;
2861	Qg90degDelay_0to4 = 12;
2862	Qg180degDelay_0to4 = 3;
2863	Qg270degDelay_0to4 = 12;
2864
2865	set_reg_29();
2866	set_reg_30();
2867	set_reg_31();
2868	set_reg_32();
2869
2870	DischargeTap16_0to3 = 1;
2871	ChargeTap16_0to3 = 8;
2872	DischargeTapn_0to3 = 7;
2873	ChargeTapn16_0to3 = 0;
2874
2875	set_reg_33();
2876	set_reg_34();
2877	}
2878	else if ((target_freq > 1000000000.0) && (target_freq <= 2000000000.0)){
2879	std::cout<<"Between 1 GHz and 2 GHz, multiply by 2"<<std::endl;
2880	// Use QuIET multiplied by 2
2881	// Step 1
2882	X1sel_32to39 = 0;
2883	X1sel_40to47 = 0;
2884	X2sel_32to36 = 0;
2885	X2sel_37to41 = 7;
2886	X4sel_32to36 = 0;
2887	X4sel_37to41 = 0;
2888
2889	set_reg_35();
2890	set_reg_36();
2891	set_reg_37();
2892	set_reg_38();
2893	set_reg_39();
2894	set_reg_40();
2895
2896	// Step 2
2897	X2sel_32to36 = 9;
2898
2899	set_reg_37();
2900
2901	// Step 3
2902	X2sel_32to36 = 25;
2903
2904	set_reg_37();
2905
2906	// Step 4
2907	//X2sel_32to36 = 16;
2908
2909	//set_reg_37();
2910
2911	try_freq = target_freq / 2;
2912
2913	// Set Quadrature Generator Charge/Discharge Taps && Delays
2914	Qg00degDelay_0to4 = 7;
2915	Qg90degDelay_0to4 = 8;
2916	Qg180degDelay_0to4 = 7;
2917	Qg270degDelay_0to4 = 5;
2918
2919	set_reg_29();
2920	set_reg_30();
2921	set_reg_31();
2922	set_reg_32();
2923
2924	DischargeTap16_0to3 = 1;
2925	ChargeTap16_0to3 = 13;
2926
2927	DischargeTapn_0to3 = 3;
2928	ChargeTapn16_0to3 = 9;
2929
2930	set_reg_33();
2931	set_reg_34();
2932	}
2933	else if ((target_freq > 2000000000.0) && (target_freq <= 4000000000.0)){
2934	std::cout<<"2-4 GHz, multiply by 4"<<std::endl;
2935	// Use QuIET frequency multiplied by 4
2936	// Step 1
2937	X1sel_32to39 = 0;
2938	X1sel_40to47 = 0;
2939	X2sel_32to36 = 0;
2940	X2sel_37to41 = 0;
2941	X4sel_32to36 = 0;
2942	X4sel_37to41 = 7;
2943
2944	set_reg_35();
2945	set_reg_36();
2946	set_reg_37();
2947	set_reg_38();
2948	set_reg_39();
2949	set_reg_40();
2950
2951	// Step 2
2952	X4sel_32to36 = 9;
2953
2954	set_reg_39();
2955
2956	// Step 3
2957	X4sel_32to36 = 25;
2958
2959	set_reg_39();
2960
2961	try_freq = target_freq / 4;
2962
2963	// Set Quadrature Generator Charge/Discharge Taps && Delays
2964	Qg00degDelay_0to4 = 0;
2965	Qg90degDelay_0to4 = 17;
2966	Qg180degDelay_0to4 = 15;
2967	Qg270degDelay_0to4 = 20;
2968
2969	set_reg_29();
2970	set_reg_30();
2971	set_reg_31();
2972	set_reg_32();
2973
2974	DischargeTap16_0to3 = 15;
2975	ChargeTap16_0to3 = 0;
2976
2977	DischargeTapn_0to3 = 10;
2978	ChargeTapn16_0to3 = 8;
2979
2980	set_reg_33();
2981	set_reg_34();
2982	}
2983	else if (target_freq > 4000000000.0){
2984	// Above 4 GHz, doesn't work
2985	args.ok = false;
2986	args.baseband_freq = target_freq;
2987	return args;
2988	}
2989
2990	Fouttx = target_freq;
2991
2992	int ret_arr[6];
2993	calc_freq_vars(Fclk, try_freq,ret_arr);
2994	Ngt3 = ret_arr[0];
2995	NorNdiv4= ret_arr[1];
2996	RorFrNpRdiv4_25to18= ret_arr[2];
2997	RorFrNpRdiv4_17to10= ret_arr[3];
2998	RorFrNpRdiv4_9to2= ret_arr[4];
2999	RorFrNpRdiv4_1to0= ret_arr[5];
3000
3001	set_reg_0();
3002	set_reg_1();
3003	set_reg_2();
3004	set_reg_3();
3005	set_reg_4();
3006
3007	args.ok = true;
3008	args.baseband_freq = target_freq;
3009	return args;
3010	//FIXME -- How do I know if the RFIC successfully attained the desired frequency?//
3011
3012	}
3013
3014	bool rfic :: set_fb_freq(double target_freq){
3015	//
3016	//@param target_freq: desired transmitter frequency in Hz
3017	//@returns (ok, actual_baseb&&_freq) where:
3018	// ok is True or False && indicates success or failure,
3019	// actual_baseb&&_freq is the RF frequency that corresponds to DC in the IF.
3020	//
3021
3022	// Go through Quadrature Generation Initialization Sequence
3023	double try_freq;
3024	if (target_freq <= 500000000.0){
3025	std::cout<<"Below 500 MHz, divide by 2"<<std::endl;
3026	// Use QuIET frequency divided by 2
3027	// Step 1
3028	X1sel_32to39_2 = 0;
3029	X1sel_40to47_2 = 62;
3030	X2sel_32to36_2 = 0;
3031	X2sel_37to41_2 = 0;
3032	X4sel_32to36_2 = 0;
3033	X4sel_37to41_2 = 0;
3034
3035	set_reg_83();
3036	set_reg_84();
3037	set_reg_85();
3038	set_reg_86();
3039	set_reg_87();
3040	set_reg_88();
3041
3042	// Step 2
3043	X1sel_40to47_2 = 63;
3044
3045	set_reg_84();
3046
3047	try_freq = target_freq * 2;
3048	}
3049	else if ((target_freq > 500000000) && (target_freq <= 1000000000)){
3050	std::cout<< "Between 500 MHz and 1 GHz"<<std::endl;
3051	// Use QuIET frequency
3052	// Step 1
3053	X1sel_32to39_2 = 1;
3054	X1sel_40to47_2 = 192;
3055	X2sel_32to36_2 = 0;
3056	X2sel_37to41_2 = 0;
3057	X4sel_32to36_2 = 0;
3058	X4sel_37to41_2 = 0;
3059
3060	set_reg_83();
3061	set_reg_84();
3062	set_reg_85();
3063	set_reg_86();
3064	set_reg_87();
3065	set_reg_88();
3066
3067	// Step 2
3068	X1sel_32to39_2 = 73;
3069
3070	set_reg_83();
3071
3072	// Step 3
3073	X1sel_32to39_2 = 201;
3074
3075	set_reg_83();
3076
3077	try_freq = target_freq;
3078
3079	// Set Quadrature Generator Charge/Discharge Taps
3080	// FIXME
3081	//ChargeTap16_0to3_2 = 7;
3082	//ChargeTapn16_0to3_2 = 5;
3083
3084	//DischargeTap16_0to3_2 = 6;
3085	//DischargeTapn16_0to3_2 = 0;
3086
3087	//set_reg_81();
3088	//set_reg_82();
3089	}
3090
3091	else if ((target_freq > 1000000000) && (target_freq <= 2000000000)){
3092	std::cout<<"Between 1 GHz and 2 GHz, multiply by 2"<<std::endl;
3093	// Use QuIET multiplied by 2
3094	// Step 1
3095	X1sel_32to39_2 = 0;
3096	X1sel_40to47_2 = 0;
3097	X2sel_32to36_2 = 0;
3098	X2sel_37to41_2 = 7;
3099	X4sel_32to36_2 = 0;
3100	X4sel_37to41_2 = 0;
3101
3102	set_reg_83();
3103	set_reg_84();
3104	set_reg_85();
3105	set_reg_86();
3106	set_reg_87();
3107	set_reg_88();
3108
3109	// Step 2
3110	X2sel_32to36_2 = 9;
3111
3112	set_reg_85();
3113
3114	// Step 3
3115	X2sel_32to36_2 = 25;
3116
3117	// Step 4
3118	//X2sel_32to36 = 16;
3119
3120	set_reg_85();
3121
3122	try_freq = target_freq / 2;
3123
3124	// Set Quadrature Generator Charge/Discharge Taps
3125	// FIXME
3126	//ChargeTap16_0to3_2 = 7;
3127	//ChargeTapn16_0to3_2 = 8;
3128
3129	//DischargeTap16_0to3_2 = 15;
3130	//DischargeTapn16_0to3_2 = 15;
3131
3132	//set_reg_81();
3133	//set_reg_82();
3134	}
3135	else if ((target_freq > 2000000000.0) && (target_freq <= 4000000000.0)){
3136	std::cout<<"2-4 GHz, multiply by 4"<<std::endl;
3137	// Use QuIET frequency multiplied by 4
3138	// Step 1
3139	X1sel_32to39_2 = 0;
3140	X1sel_40to47_2 = 0;
3141	X2sel_32to36_2 = 0;
3142	X2sel_37to41_2 = 0;
3143	X4sel_32to36_2 = 0;
3144	X4sel_37to41_2 = 7;
3145
3146	set_reg_83();
3147	set_reg_84();
3148	set_reg_85();
3149	set_reg_86();
3150	set_reg_87();
3151	set_reg_88();
3152
3153	// Step 2
3154	X4sel_32to36_2 = 9;
3155
3156	set_reg_87();
3157
3158	// Step 3
3159	X4sel_32to36_2 = 25;
3160
3161	set_reg_87();
3162
3163	try_freq = target_freq / 4;
3164
3165	// Set Quadrature Generator Charge/Discharge Taps
3166	// FIXME
3167	//ChargeTap16_0to3_2 = 15;
3168	//ChargeTapn16_0to3_2 = 15;
3169
3170	//DischargeTap16_0to3_2 = 6;
3171	//DischargeTapn16_0to3_2 = 4;
3172
3173	//set_reg_81();
3174	//set_reg_82();
3175	}
3176	else if (target_freq > 4000000000.0){
3177	// Above 4 GHz, doesn't work
3178	return false;
3179	}
3180	Foutfb = target_freq;
3181	int ret_arr[6];
3182	calc_freq_vars(Fclk, try_freq,ret_arr);
3183	Ngt3_2 = ret_arr[0];
3184	NorNdiv4_2= ret_arr[1];
3185	RorFrNpRdiv4_25to18_2= ret_arr[2];
3186	RorFrNpRdiv4_17to10_2= ret_arr[3];
3187	RorFrNpRdiv4_9to2_2= ret_arr[4];
3188	RorFrNpRdiv4_1to0_2= ret_arr[5];
3189
3190
3191	set_reg_48();
3192	set_reg_49();
3193	set_reg_50();
3194	set_reg_51();
3195	set_reg_52();
3196
3197	return true;
3198	//FIXME -- How do I know if the RFIC successfully attained the desired frequency?//
3199	}
3200
3201	/////////////////////////////////////////
3202
3203	bool rfic :: set_rx_phase(int phsh){
3204	//
3205	//@param phsh{ desired phase shift in degrees
3206	//@returns (ok) where{
3207	// ok is True or False and indicates success or failure
3208	//
3209	double synth_freq;
3210	phsh = phsh % 360;
3211
3212	if (Foutrx <= 500000000.0)
3213	synth_freq = Foutrx * 2;
3214	else if ( (Foutrx > 500000000.0) and (Foutrx <= 1000000000.0))
3215	synth_freq = Foutrx;
3216	else if ( (Foutrx > 1000000000.0) and (Foutrx < 2000000000.0))
3217	synth_freq = Foutrx / 2;
3218	else if (Foutrx > 2000000000.0)
3219	synth_freq = Foutrx / 4;
3220
3221	int ret_arr[6];
3222	calc_phase_vars(Fclk, synth_freq,phsh,ret_arr);
3223	Qu_tx_Ngt3_3 = ret_arr[0];
3224	NorNdiv4_phsh_3= ret_arr[1];
3225	RorFrNpRdiv4_phsh_25to18_3= ret_arr[2];
3226	RorFrNpRdiv4_phsh_17to10_3= ret_arr[3];
3227	RorFrNpRdiv4_phsh_9to2_3= ret_arr[4];
3228	RorFrNpRdiv4_phsh_1to0_3= ret_arr[5];
3229
3230
3231	set_reg_109();
3232	set_reg_110();
3233	set_reg_111();
3234	set_reg_112();
3235	set_reg_113();
3236
3237	return true;
3238	//FIXME -- How do I know if the RFIC successfully attained the desired phase?//
3239	}
3240
3241	bool rfic :: set_tx_phase(int phsh){
3242	//
3243	//@param phsh{ desired phase shift in degrees
3244	//@returns (ok) where{
3245	// ok is True or False and indicates success or failure
3246	//
3247	double synth_freq;
3248	phsh = phsh % 360;
3249
3250	if (Fouttx <= 500000000.0)
3251	synth_freq = Fouttx * 2;
3252	else if ( (Fouttx > 500000000.0) and (Fouttx <= 1000000000.0))
3253	synth_freq = Fouttx;
3254	else if ( (Fouttx > 1000000000.0) and (Fouttx < 2000000000.0))
3255	synth_freq = Fouttx / 2;
3256	else if (Fouttx > 2000000000)
3257	synth_freq = Fouttx / 4;
3258
3259	int ret_arr[6];
3260	calc_phase_vars(Fclk, synth_freq,phsh,ret_arr);
3261	Qu_tx_Ngt3_3 = ret_arr[0];
3262	NorNdiv4_phsh_3= ret_arr[1];
3263	RorFrNpRdiv4_phsh_25to18_3= ret_arr[2];
3264	RorFrNpRdiv4_phsh_17to10_3= ret_arr[3];
3265	RorFrNpRdiv4_phsh_9to2_3= ret_arr[4];
3266	RorFrNpRdiv4_phsh_1to0_3= ret_arr[5];
3267
3268	set_reg_5();
3269	set_reg_6();
3270	set_reg_7();
3271	set_reg_8();
3272	set_reg_9();
3273
3274	//FIXME -- How do I know if the RFIC successfully attained the desired phase?//
3275	return true;
3276	}
3277
3278	bool rfic :: set_fb_phase(int phsh){
3279	//
3280	//@param phsh{ desired phase shift in degrees
3281	//@returns (ok) where{
3282	// ok is True or False and indicates success or failure
3283	//
3284	double synth_freq;
3285	phsh = phsh % 360;
3286
3287	if (Foutfb <= 500000000.0)
3288	synth_freq = Foutfb * 2;
3289	else if ( (Foutfb > 500000000.0) and (Foutfb <= 1000000000.0))
3290	synth_freq = Foutfb;
3291	else if ( (Foutfb > 1000000000.0) and (Foutfb < 2000000000.0))
3292	synth_freq = Foutfb / 2;
3293	else if (Foutfb > 2000000000.0)
3294	synth_freq = Foutfb / 4;
3295
3296
3297	int ret_arr[6];
3298	calc_phase_vars(Fclk, synth_freq,phsh,ret_arr);
3299	Qu_tx_Ngt3_3 = ret_arr[0];
3300	NorNdiv4_phsh_3= ret_arr[1];
3301	RorFrNpRdiv4_phsh_25to18_3= ret_arr[2];
3302	RorFrNpRdiv4_phsh_17to10_3= ret_arr[3];
3303	RorFrNpRdiv4_phsh_9to2_3= ret_arr[4];
3304	RorFrNpRdiv4_phsh_1to0_3= ret_arr[5];
3305
3306	set_reg_53();
3307	set_reg_54();
3308	set_reg_55();
3309	set_reg_56();
3310	set_reg_57();
3311
3312	//FIXME -- How do I know if the RFIC successfully attained the desired phase?//
3313	return true;
3314	}
3315
3316	bool rfic :: set_rx_bw(float bw){
3317	//
3318	//@param bw{ desired bandwidth in Hz
3319	//
3320	// Available bandwidth{ 4.25 kHz to 14 MHz (baseband)
3321	// FIXME
3322	std::cout<<"Desired bandwidth :"<< bw<<std::endl;
3323	if (bw <= 5250){
3324	// Set BW to 3.532 kHz
3325	rx_rfp = 3;
3326	rx_cp_12to8 = 31;
3327	rx_cp_7to0 = 240;
3328
3329	rx_rv = 7;
3330	rx_cv_10to3 = 254;
3331	rx_cv_2to0 = 0;
3332
3333	rx_rq = 7;
3334	rx_cq_9to8 = 3;
3335	rx_cq_7to0 = 240;
3336	}
3337
3338	else if (bw > 5250 and bw <= 10500){
3339	// Set BW to 7.065 kHz
3340	rx_rfp = 3;
3341	rx_cp_12to8 = 31;
3342	rx_cp_7to0 = 240;
3343
3344	rx_rv = 5;
3345	rx_cv_10to3 = 254;
3346	rx_cv_2to0 = 0;
3347
3348	rx_rq = 5;
3349	rx_cq_9to8 = 3;
3350	rx_cq_7to0 = 240;
3351	}
3352	else if (bw > 10500 and bw <= 21000){
3353	// Set BW to 14.130 kHz
3354	rx_rfp = 2;
3355	rx_cp_12to8 = 31;
3356	rx_cp_7to0 = 240;
3357
3358	rx_rv = 4;
3359	rx_cv_10to3 = 254;
3360	rx_cv_2to0 = 0;
3361
3362	rx_rq = 4;
3363	rx_cq_9to8 = 3;
3364	rx_cq_7to0 = 240;
3365	}
3366
3367	else if (bw > 21000 and bw <= 42000){
3368	// Set BW to 28.259 kHz
3369	rx_rfp = 2;
3370	rx_cp_12to8 = 15;
3371	rx_cp_7to0 = 240;
3372
3373	rx_rv = 3;
3374	rx_cv_10to3 = 254;
3375	rx_cv_2to0 = 0;
3376
3377	rx_rq = 3;
3378	rx_cq_9to8 = 3;
3379	rx_cq_7to0 = 240;
3380	}
3381	else if (bw > 42000 and bw <= 84500){
3382	// Set BW to 56.518 kHz
3383	rx_rfp = 2;
3384	rx_cp_12to8 = 7;
3385	rx_cp_7to0 = 240;
3386
3387	rx_rv = 2;
3388	rx_cv_10to3 = 254;
3389	rx_cv_2to0 = 0;
3390
3391	rx_rq = 2;
3392	rx_cq_9to8 = 3;
3393	rx_cq_7to0 = 240;
3394	}
3395	else if (bw > 84500 and bw <= 169500){
3396	// Set BW to 113.036 kHz
3397	rx_rfp = 2;
3398	rx_cp_12to8 = 3;
3399	rx_cp_7to0 = 240;
3400
3401	rx_rv = 1;
3402	rx_cv_10to3 = 254;
3403	rx_cv_2to0 = 0;
3404
3405	rx_rq = 1;
3406	rx_cq_9to8 = 3;
3407	rx_cq_7to0 = 240;
3408	}
3409	else if (bw > 169500 and bw <= 339000){
3410	// Set BW to 226.072 kHz
3411	rx_rfp = 2;
3412	rx_cp_12to8 = 1;
3413	rx_cp_7to0 = 240;
3414
3415	rx_rv = 1;
3416	rx_cv_10to3 = 126;
3417	rx_cv_2to0 = 0;
3418
3419	rx_rq = 1;
3420	rx_cq_9to8 = 1;
3421	rx_cq_7to0 = 240;
3422	}
3423	else if (bw > 339000 and bw <= 667000){
3424	// Set BW to 452.145 kHz
3425	rx_rfp = 1;
3426	rx_cp_12to8 = 1;
3427	rx_cp_7to0 = 240;
3428
3429	rx_rv = 0;
3430	rx_cv_10to3 = 254;
3431	rx_cv_2to0 = 0;
3432
3433	rx_rq = 1;
3434	rx_cq_9to8 = 0;
3435	rx_cq_7to0 = 240;
3436	}
3437	else if (bw > 667000 and bw <= 1356000){
3438	// Set BW to 904.289 kHz
3439	rx_rfp = 1;
3440	rx_cp_12to8 = 0;
3441	rx_cp_7to0 = 240;
3442
3443	rx_rv = 0;
3444	rx_cv_10to3 = 126;
3445	rx_cv_2to0 = 0;
3446
3447	rx_rq = 0;
3448	rx_cq_9to8 = 3;
3449	rx_cq_7to0 = 240;
3450	}
3451	else if (bw > 1356000 and bw <= 2712500){
3452	// Set BW to 1808.579 kHz
3453	rx_rfp = 1;
3454	rx_cp_12to8 = 0;
3455	rx_cp_7to0 = 112;
3456
3457	rx_rv = 0;
3458	rx_cv_10to3 = 62;
3459	rx_cv_2to0 = 0;
3460
3461	rx_rq = 0;
3462	rx_cq_9to8 = 1;
3463	rx_cq_7to0 = 240;
3464	}
3465	else if (bw > 2712500 and bw <= 5425500){
3466	// Set BW to 3617.157 kHz
3467	rx_rfp = 0;
3468	rx_cp_12to8 = 0;
3469	rx_cp_7to0 = 112;
3470
3471	rx_rv = 0;
3472	rx_cv_10to3 = 30;
3473	rx_cv_2to0 = 0;
3474
3475	rx_rq = 0;
3476	rx_cq_9to8 = 0;
3477	rx_cq_7to0 = 240;
3478	}
3479	else if (bw > 5425500 and bw <= 10851000){
3480	// Set BW to 7234.315 kHz
3481	rx_rfp = 0;
3482	rx_cp_12to8 = 0;
3483	rx_cp_7to0 = 48;
3484
3485	rx_rv = 0;
3486	rx_cv_10to3 = 14;
3487	rx_cv_2to0 = 0;
3488
3489	rx_rq = 0;
3490	rx_cq_9to8 = 0;
3491	rx_cq_7to0 = 112;
3492	}
3493	else if (bw > 10851000){
3494	// Set BW to 14468.630 kHz
3495	rx_rfp = 0;
3496	rx_cp_12to8 = 0;
3497	rx_cp_7to0 = 16;
3498
3499	rx_rv = 0;
3500	rx_cv_10to3 = 6;
3501	rx_cv_2to0 = 0;
3502
3503	rx_rq = 0;
3504	rx_cq_9to8 = 0;
3505	rx_cq_7to0 = 48;
3506	}
3507	set_reg_198();
3508	set_reg_199();
3509	set_reg_200();
3510	set_reg_201();
3511	set_reg_202();
3512	set_reg_203();
3513	set_reg_204();
3514	return true; //always returning true..may have to change this
3515
3516	}
3517
3518
3519
3520	bool rfic :: set_tx_bw(float bw){
3521	//
3522	//@param bw{ desired bandwidth in Hz
3523	//
3524	// Available bandwidth{ 6.25 kHz to 14+ MHz (baseband)
3525	// FIXME
3526	std::cout<<"Desired bandwidth :"<< bw<<std::endl;
3527	if (bw <= 20000){
3528	// Set BW to 12.5 kHz
3529	tx_p1_bw = 3;
3530	tx_p2_bw2 = 15;
3531	}
3532	else if (bw > 20000 and bw <= 37500){
3533	// Set BW to 25 kHz
3534	tx_p1_bw = 3;
3535	tx_p2_bw2 = 7;
3536	}
3537	else if (bw > 37500 and bw <= 75000){
3538	// Set BW to 50 kHz
3539	tx_p1_bw = 3;
3540	tx_p2_bw2 = 3;
3541	}
3542	else if (bw > 75000 and bw <= 150000){
3543	// Set BW to 100 kHz
3544	tx_p1_bw = 3;
3545	tx_p2_bw2 = 1;
3546	}
3547	else if (bw > 150000 and bw <= 425000){
3548	// Set BW to 200 kHz
3549	tx_p1_bw = 3;
3550	tx_p2_bw2 = 0;
3551	}
3552	else if (bw > 425000 and bw <= 1125000){
3553	// Set BW to 750 kHz
3554	tx_p1_bw = 1;
3555	tx_p2_bw2 = 15;
3556	}
3557	else if (bw > 1125000 and bw <= 2250000){
3558	// Set BW to 1.5 MHz
3559	tx_p1_bw = 1;
3560	tx_p2_bw2 = 7;
3561	}
3562	else if (bw > 2250000 and bw <= 4500000){
3563	// Set BW to 3 MHz
3564	tx_p1_bw = 1;
3565	tx_p2_bw2 = 3;
3566	}
3567	else if (bw > 4500000 and bw <= 9000000){
3568	// Set BW to 6 MHz
3569	tx_p1_bw = 1;
3570	tx_p2_bw2 = 1;
3571	}
3572	else if (bw > 9000000 and bw <= 13000000){
3573	// Set BW to 12 MHz
3574	tx_p1_bw = 1;
3575	tx_p2_bw2 = 0;
3576	}
3577	else if (bw > 13000000){
3578	// Set BW to 14+ MHz
3579	tx_p1_bw = 0;
3580	tx_p2_bw2 = 0;
3581	}
3582	set_reg_173();
3583	set_reg_174();
3584	return true; //always returning true..may have to change this
3585	}
3586
3587	void rfic :: set_fb_bw(float bw){
3588	//
3589	//@param bw{ desired bandwidth in Hz
3590	//
3591	// Available bandwidth{ 5 MHz to 14+ MHz (baseband)
3592	// FIXME
3593	std::cout<<"Desired bandwidth :"<< bw<<std::endl;
3594	if (bw <= 7500000){
3595	// Set BW to 5 MHz
3596	tx_bb_fdbk_bw = 3;
3597	}
3598	else if (bw > 7500000 and bw <= 12000000){
3599	// Set BW to 10 MHz
3600	tx_bb_fdbk_bw = 1;
3601	}
3602	else if (bw > 12000000){
3603	// Set BW to 14+ MHz
3604	tx_bb_fdbk_bw = 0;
3605	}
3606	set_reg_156();
3607	}
3608
3609	void rfic :: enable_tx_fb(){
3610	//
3611	// Enable transmitter feedback to RX port for DC offset correction, etc.
3612	//
3613	// FIXME
3614	std::cout<<"Enabling Transmit Feedback"<<std::endl;
3615
3616	// Disable RX Filter
3617	rx_foe = 0;
3618	set_reg_196();
3619
3620	// Enable Baseband Feedback, TX I and Q via RX I and Q
3621	tx_bb_fdbk_en = 3;
3622	set_reg_157();
3623
3624	// Disable Baseband Feedback Calibration
3625	// FIXME
3626	//tx_bb_fdbk_cal_en = 0
3627
3628	// Enable Baseband Feedback Cartesian Forward Path
3629	tx_bb_fdbk_cart_fwd_en = 1;
3630	set_reg_156();
3631
3632	// Enable Cartesian Feedback Path
3633	tx_cart_en = 1;
3634	set_reg_160();
3635
3636	// Enable Cartesian Feedback
3637	CartesianFeedbackpathenable = 1;
3638
3639	// Enable Cartesian Feedback Path DCOC
3640	CartesianFeedbackpathDCOCenable = 1;
3641	set_reg_166();
3642
3643	// Set Cartesian Feedback Path Amplifier Gain
3644	CartesianFBpathAmp1Gain = 0;
3645	CartesianFBpathAmp2Gain = 0;
3646	CartesianFBpathAmp3Gain = 0;
3647	CartesianFBpathAmp4Gain = 0;
3648	set_reg_169();
3649
3650	// Enable Cartesian Feedback Path Zero
3651	CartesianFBpathZeroEnable = 1;
3652	set_reg_170();
3653	}
3654
3655	void rfic :: disable_tx_fb(){
3656	//
3657	// Disable transmitter feedback to RX port
3658	//
3659	// FIXME
3660	std::cout<<"Disabling Transmit Feedback"<<std::endl;
3661
3662	// Enable RX Filter
3663	rx_foe = 1;
3664	set_reg_196();
3665
3666	// Disable Baseband Feedback
3667	tx_bb_fdbk_en = 0;
3668	set_reg_157();
3669
3670	// Enable Baseband Feedback Calibration
3671	// FIXME
3672	//tx_bb_fdbk_cal_en = 1
3673
3674	// Disable Baseband Feedback Cartesian Forward Path
3675	tx_bb_fdbk_cart_fwd_en = 0;
3676	set_reg_156();
3677
3678	// Disable Cartesian Feedback Path
3679	tx_cart_en = 0;
3680	set_reg_160();
3681
3682	// Disable Cartesian Feedback
3683	CartesianFeedbackpathenable = 0;
3684
3685	// Disable Cartesian Feedback Path DCOC
3686	CartesianFeedbackpathDCOCenable = 0;
3687	set_reg_166();
3688
3689	// Set Cartesian Feedback Path Amplifier Gain
3690	CartesianFBpathAmp1Gain = 3;
3691	CartesianFBpathAmp2Gain = 3;
3692	CartesianFBpathAmp3Gain = 3;
3693	CartesianFBpathAmp4Gain = 3;
3694	set_reg_169();
3695
3696	// Disable Cartesian Feedback Path Zero
3697	CartesianFBpathZeroEnable = 0;
3698	set_reg_170();
3699	}
3700
3701
3702	int rfic :: RSSI_fade(){
3703	// Return fade, clip from the two RX-side ADCs.
3704	//@returns fade, clip
3705	// variables proportional to how much fading (low signal strength)
3706	// or clipping (high signal strength) is going on
3707
3708	// Turn off test mux
3709	int fade;
3710	TestMuxBufferEnable = 0; //Disable Test Mux Buffer
3711	TestMuxEnable = 0; //Disable Test Mux
3712	TestMuxSetting = 0; //Four Output Description (Test1, Test2, Test3, Test4)
3713	set_reg_222();
3714
3715	// Turn on on-channel detectors
3716	// Off-channel doesn't work - leave it off
3717	rx_onchen = 1; //Enables on-channel detector.
3718	rx_offchen = 0; //Disables off-channel detector
3719	set_reg_196();
3720
3721	// Set clip and fade thresholds
3722	rx_offch = 1; //Sets the Clip Threshold for the Off-channel Detector
3723	rx_onchf = 0; //Sets the Fade Threshold for the On-channel Detector relative to the On-channel clip point.
3724	rx_onchc = 2; //Sets the Clip Threshold for the On-channel Detector
3725	set_reg_197();
3726
3727	fade = usrp()->read_aux_adc(d_which, 0);
3728	return fade;
3729	}
3730	int rfic :: RSSI_clip(){
3731	// Return fade, clip from the two RX-side ADCs.
3732	//@returns fade, clip
3733	// variables proportional to how much fading (low signal strength)
3734	// or clipping (high signal strength) is going on
3735
3736	// Turn off test mux
3737	int clip;
3738	TestMuxBufferEnable = 0; //Disable Test Mux Buffer
3739	TestMuxEnable = 0; //Disable Test Mux
3740	TestMuxSetting = 0; //Four Output Description (Test1, Test2, Test3, Test4)
3741	set_reg_222();
3742
3743	// Turn on on-channel detectors
3744	// Off-channel doesn't work - leave it off
3745	rx_onchen = 1; //Enables on-channel detector.
3746	rx_offchen = 0; //Disables off-channel detector
3747	set_reg_196();
3748
3749	// Set clip and fade thresholds
3750	rx_offch = 1; //Sets the Clip Threshold for the Off-channel Detector
3751	rx_onchf = 0; //Sets the Fade Threshold for the On-channel Detector relative to the On-channel clip point.
3752	rx_onchc = 2; //Sets the Clip Threshold for the On-channel Detector
3753	set_reg_197();
3754
3755	clip = usrp()->read_aux_adc(d_which, 1);
3756	return clip;
3757	}
3758
3759
3760	/*****************************************************************************/
3761
3762
3763	struct rfic_table_entry {
3764	rfic_key key;
3765	boost::weak_ptr<rfic> value;
3766
3767	rfic_table_entry(const rfic_key &_key, boost::weak_ptr<rfic> _value)
3768	: key(_key), value(_value) {}
3769	};
3770
3771	typedef std::vector<rfic_table_entry> rfic_table;
3772
3773	static boost::mutex s_table_mutex;
3774	static rfic_table s_table;
3775
3776	static rfic_sptr
3777	_get_or_make_rfic(usrp_basic_sptr usrp, int which)
3778	{
3779	rfic_key key = {usrp->serial_number(), which};
3780
3781	boost::mutex::scoped_lock guard(s_table_mutex);
3782
3783	for (rfic_table::iterator p = s_table.begin(); p != s_table.end();){
3784	if (p->value.expired()) // weak pointer is now dead
3785	p = s_table.erase(p); // erase it
3786	else {
3787	if (key == p->key){ // found it
3788	return rfic_sptr(p->value);
3789	}
3790	else
3791	++p; // keep looking
3792	}
3793	}
3794
3795	// We don't have the rfic we're looking for
3796
3797	// create a new one and stick it in the table.
3798	rfic_sptr r(new rfic(usrp, which));
3799	rfic_table_entry t(key, r);
3800	s_table.push_back(t);
3801
3802	return r;
3803	}
3804
3805
3806	/*****************************************************************************/
3807
3808
3809
3810	db_rfic_base::db_rfic_base(usrp_basic_sptr usrp, int which)
3811	: db_base(usrp, which)
3812	{
3813	/*
3814	* Abstract base class for all rfic boards.
3815	*
3816	* Derive board specific subclasses from db_rfic_base_{tx,rx}
3817	*
3818	* @param usrp: instance of usrp.source_c
3819	* @param which: which side: 0 or 1 corresponding to side A or B respectively
3820	* @type which: int
3821	*/
3822
3823	d_rfic = _get_or_make_rfic(usrp, which);
3824	}
3825
3826	db_rfic_base::~db_rfic_base()
3827	{
3828	}
3829
3830
3831	bool
3832	db_rfic_base::is_quadrature()
3833	{
3834	/*
3835	* Return True if this board requires both I & Q analog channels.
3836	*
3837	* This bit of info is useful when setting up the USRP Rx mux register.
3838	*/
3839	return true;
3840	}
3841
3842
3843	double
3844	db_rfic_base::freq_min()
3845	{
3846	return 2.5e6;
3847	}
3848
3849
3850	double
3851	db_rfic_base::freq_max()
3852	{
3853	return 1e8;
3854	}
3855
3856
3857	void
3858	db_rfic_base::shutdown_common()
3859	{
3860	// If the usrp_basic in the rfic is the same as the usrp_basic
3861	// in the daughterboard, shutdown the rfic now (when only one of Tx
3862	// and Rx is open, this is always true).
3863
3864	if (d_rfic->usrp() == usrp()){
3865	//std::cerr << "db_rfic_base::shutdown_common: same -> shutting down\n";
3866	d_rfic->shutdown();
3867	}
3868	else {
3869	//std::cerr << "db_rfic_base::shutdown_common: different -> ignoring\n";
3870	}
3871	}
3872
3873	/******************************************************************************************************/
3874
3875	////////////
3876	db_rfic_tx::db_rfic_tx(usrp_basic_sptr usrp, int which)
3877	: db_rfic_base(usrp, which)
3878	{
3879
3880	//select_tx_antenna(abc);
3881	d_rfic->set_reg_0();
3882	d_rfic->set_reg_1();
3883	d_rfic->set_reg_2();
3884	d_rfic->set_reg_3();
3885	d_rfic->set_reg_4();
3886	d_rfic->set_reg_5();
3887	d_rfic->set_reg_6();
3888	d_rfic->set_reg_7();
3889	d_rfic->set_reg_8();
3890	d_rfic->set_reg_9();
3891	d_rfic->set_reg_10();
3892	d_rfic->set_reg_12();
3893	d_rfic->set_reg_13();
3894	d_rfic->set_reg_14();
3895	d_rfic->set_reg_15();
3896	d_rfic->set_reg_16();
3897	d_rfic->set_reg_17();
3898	d_rfic->set_reg_18();
3899	d_rfic->set_reg_19();
3900	d_rfic->set_reg_20();
3901	d_rfic->set_reg_21();
3902	d_rfic->set_reg_22();
3903	d_rfic->set_reg_23();
3904	d_rfic->set_reg_24();
3905	d_rfic->set_reg_29();
3906	d_rfic->set_reg_30();
3907	d_rfic->set_reg_31();
3908	d_rfic->set_reg_32();
3909	d_rfic->set_reg_33();
3910	d_rfic->set_reg_34();
3911	d_rfic->set_reg_35();
3912	d_rfic->set_reg_36();
3913	d_rfic->set_reg_37();
3914	d_rfic->set_reg_38();
3915	d_rfic->set_reg_39();
3916	d_rfic->set_reg_40();
3917	d_rfic->set_reg_41();
3918	d_rfic->set_reg_42();
3919	d_rfic->set_reg_43();
3920	d_rfic->set_reg_156();
3921	d_rfic->set_reg_157();
3922	d_rfic->set_reg_158();
3923	d_rfic->set_reg_159();
3924	d_rfic->set_reg_160();
3925	d_rfic->set_reg_161();
3926	d_rfic->set_reg_162();
3927	d_rfic->set_reg_163();
3928	d_rfic->set_reg_164();
3929	d_rfic->set_reg_165();
3930	d_rfic->set_reg_166();
3931	d_rfic->set_reg_167();
3932	d_rfic->set_reg_168();
3933	d_rfic->set_reg_169();
3934	d_rfic->set_reg_170();
3935	d_rfic->set_reg_171();
3936	d_rfic->set_reg_172();
3937	d_rfic->set_reg_173();
3938	d_rfic->set_reg_174();
3939	d_rfic->set_reg_175();
3940	d_rfic->set_reg_176();
3941	d_rfic->set_reg_177();
3942	d_rfic->set_reg_178();
3943	d_rfic->set_reg_179();
3944	d_rfic->set_reg_180();
3945	d_rfic->set_reg_181();
3946
3947	// Get digital block out of digital reset state
3948	d_rfic->Rst_n_async = 1;
3949	d_rfic->set_reg_24();
3950
3951	// Turn on forward baseband reference section
3952	d_rfic->tx_bb_en = 1;
3953	// FIXME
3954	//d_rfic->set_reg_156();
3955
3956	// Unroutes the Cartesian error signal through the BB Correction feedback
3957	// FIXME
3958	d_rfic->tx_bb_fdbk_cart_err_en = 0;
3959
3960	// Routes the Cartesian feedback signal through the BB Correction feedback
3961	// FIXME
3962	d_rfic->tx_bb_fdbk_cart_fb_en = 1;
3963	d_rfic->set_reg_156();
3964
3965	// Turn on baseband feedback section
3966	// FIXME
3967	//d_rfic->tx_bb_fdbk_en = 3;
3968	//d_rfic->set_reg_157();
3969
3970	// Turn on forward RF transmit path
3971	d_rfic->RFForwardPathEnable_toMUX = 1;
3972	d_rfic->set_reg_175();
3973
3974	// Turn on Cartesian FB path switch to forward summer
3975	d_rfic->CartesianFBpathSwitchtoforwardSummer = 1;
3976	d_rfic->set_reg_168();
3977
3978	// Turn on Cartesian zero
3979	d_rfic->CartesianFBpathZeroEnable = 1;
3980	d_rfic->set_reg_170();
3981
3982	// Select TX output path, default tx1
3983	// FIXME
3984	d_rfic->tx_output_channel_sel = 2;
3985	//d_rfic->tx_output_channel_sel = 1;
3986	d_rfic->set_reg_172();
3987
3988	// Set TX Channel 1 Gain
3989	// The gain control on TX channel 1 is controlled by this DAC
3990	// The maximum voltage is 2.2 volts, which corresponds to 2750
3991	// This controls about 35 dB of gain ONLY ON TX 1
3992	d_rfic->usrp()->write_aux_dac(d_rfic->d_which, 3, 2750);
3993
3994
3995	// POR On. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
3996	d_rfic->Clk_driver_en = 1;
3997
3998	// POR On
3999	d_rfic->qu_reg_en = 1;
4000
4001	// POR On
4002	d_rfic->qq_reg_en = 1;
4003
4004	// POR Off
4005	d_rfic->win_rst = 0;
4006
4007	// POR On
4008	d_rfic->fineEn = 0;
4009
4010	// POR Off
4011	d_rfic->fineEnb = 1;
4012
4013	// POR On
4014	//d_rfic->rsffEn = 0;
4015
4016	// POR On
4017	d_rfic->dl_en = 1;
4018
4019	// POR On
4020	d_rfic->cp_en = 1;
4021
4022	d_rfic->set_reg_20();
4023	d_rfic->set_reg_21();
4024	}
4025
4026	db_rfic_tx::~db_rfic_tx()
4027	{
4028	// print "rfic_base_tx.__del__"
4029	// Power down
4030
4031	// Turn off output channel
4032	d_rfic->tx_output_channel_sel = 0;
4033	d_rfic->set_reg_172();
4034
4035	// Turn off forward RF transmit path
4036	d_rfic->RFForwardPathEnable_toMUX = 0;
4037	d_rfic->set_reg_17();
4038
4039	// Turn off forward baseband reference section
4040	d_rfic->tx_bb_en = 0;
4041	d_rfic->set_reg_156();
4042
4043	// Unroutes the Cartesian error signal through the BB Correction feedback
4044	// FIXME
4045	d_rfic->tx_bb_fdbk_cart_err_en = 0;
4046
4047	// Unroutes the Cartesian feedback signal through the BB Correction feedback
4048	d_rfic->tx_bb_fdbk_cart_fb_en = 0;
4049	d_rfic->set_reg_156();
4050
4051	// Turn off Cartesian FB path switch to forward summer
4052	d_rfic->CartesianFBpathSwitchtoforwardSummer = 0;
4053	d_rfic->set_reg_168();
4054
4055	// Turn off Cartesian zero
4056	d_rfic->CartesianFBpathZeroEnable = 0;
4057	d_rfic->set_reg_170();
4058
4059	// Turn off baseband feedback section
4060	// FIXME
4061	//d_rfic->tx_bb_fdbk_en = 0;
4062	//d_rfic->set_reg_157()
4063
4064	// POR Off. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
4065	d_rfic->Clk_driver_en = 0;
4066
4067	// POR Off
4068	d_rfic->qu_reg_en = 0;
4069
4070	// POR Off
4071	d_rfic->qq_reg_en = 0;
4072
4073	// POR Off
4074	d_rfic->win_rst = 0;
4075
4076	// POR Off
4077	d_rfic->fineEn = 0;
4078
4079	// POR Off
4080	d_rfic->fineEnb = 0;
4081
4082	// POR Off
4083	//d_rfic->rsffEn = 0;
4084
4085	// POR Off
4086	d_rfic->dl_en = 0;
4087
4088	// POR Off
4089	d_rfic->cp_en = 0;
4090
4091	d_rfic->set_reg_20();
4092	d_rfic->set_reg_21();
4093
4094	// Put digital block in digital reset state
4095	d_rfic->Rst_n_async = 0;
4096	d_rfic->set_reg_24();
4097	shutdown();
4098
4099
4100	}
4101
4102	bool
4103	db_rfic_tx::select_tx_antenna(std::string which_antenna){
4104	//
4105	//Specify which antenna port to use for transmission.
4106	//@param which_antenna: either 'tx1', 'tx2' or 'tx3'
4107	//
4108	if (which_antenna == "tx1"){
4109	d_rfic->tx_output_channel_sel = 1;
4110	d_rfic->set_reg_172();
4111	}
4112	else if (which_antenna == "tx2"){
4113	d_rfic->tx_output_channel_sel = 2;
4114	d_rfic->set_reg_172();
4115	}
4116	else if (which_antenna == "tx3"){
4117	d_rfic->tx_output_channel_sel = 4;
4118	d_rfic->set_reg_172();
4119	}
4120	else{
4121	std::cout<< "which_antenna must be either tx1/0 , tx2/1 or tx3/2"<<std::endl;
4122	return false;
4123	}
4124
4125	return true;
4126	}
4127
4128
4129	bool
4130	db_rfic_tx::select_tx_antenna(int which_antenna){
4131	//
4132	//Specify which antenna port to use for transmission.
4133	//@param which_antenna: either 'tx1', 'tx2' or 'tx3'
4134	//
4135	if (which_antenna == 0){
4136	d_rfic->tx_output_channel_sel = 1;
4137	d_rfic->set_reg_172();
4138	}
4139	else if (which_antenna == 1){
4140	d_rfic->tx_output_channel_sel = 2;
4141	d_rfic->set_reg_172();
4142	}
4143	else if (which_antenna == 2){
4144	d_rfic->tx_output_channel_sel = 4;
4145	d_rfic->set_reg_172();
4146	}
4147	else{
4148	std::cout<< "which_antenna must be either tx1/0 , tx2/1 or tx3/2"<<std::endl;
4149	return false;
4150	}
4151
4152	return true;
4153	}
4154
4155	void
4156	db_rfic_tx::shutdown()
4157	{
4158	if (!d_is_shutdown){
4159	d_is_shutdown = true;
4160	shutdown_common();
4161	}
4162	}
4163
4164	float
4165	db_rfic_tx::gain_min()
4166	{
4167	return 0.0;
4168	}
4169
4170	float
4171	db_rfic_tx::gain_max()
4172	{
4173	return 45.0;
4174	}
4175
4176	bool
4177	db_rfic_tx::set_gain(float gain)
4178	{
4179	return d_rfic->set_tx_gain(gain);
4180	}
4181
4182	struct freq_result_t
4183	db_rfic_tx::set_freq(double target_frequency)
4184	{
4185	return d_rfic->set_tx_freq(target_frequency);
4186	}
4187
4188	bool
4189	db_rfic_tx::set_phase(int phase)
4190	{
4191	return d_rfic->set_tx_phase(phase);
4192	}
4193
4194	bool
4195	db_rfic_tx::set_bw(float bw)
4196	{
4197	return d_rfic->set_tx_bw(bw);
4198	}
4199
4200	bool
4201	db_rfic_tx::spectrum_inverted()
4202	{
4203	return true;
4204	}
4205
4206	float
4207	db_rfic_tx::gain_db_per_step()
4208	{
4209	return d_rfic->usrp()->pga_db_per_step();
4210	}
4211
4212
4213	db_rfic_rx::db_rfic_rx(usrp_basic_sptr usrp, int which)
4214	: db_rfic_base(usrp, which)
4215	{
4216	std::string abc = "MIX5";
4217	this->select_rx_antenna(abc);
4218	d_rfic->set_reg_48();
4219	d_rfic->set_reg_49();
4220	d_rfic->set_reg_50();
4221	d_rfic->set_reg_51();
4222	d_rfic->set_reg_52();
4223	d_rfic->set_reg_53();
4224	d_rfic->set_reg_54();
4225	d_rfic->set_reg_55();
4226	d_rfic->set_reg_56();
4227	d_rfic->set_reg_57();
4228	d_rfic->set_reg_58();
4229	d_rfic->set_reg_60();
4230	d_rfic->set_reg_61();
4231	d_rfic->set_reg_62();
4232	d_rfic->set_reg_63();
4233	d_rfic->set_reg_64();
4234	d_rfic->set_reg_65();
4235	d_rfic->set_reg_66();
4236	d_rfic->set_reg_67();
4237	d_rfic->set_reg_68();
4238	d_rfic->set_reg_69();
4239	d_rfic->set_reg_70();
4240	d_rfic->set_reg_71();
4241	d_rfic->set_reg_72();
4242	d_rfic->set_reg_77();
4243	d_rfic->set_reg_78();
4244	d_rfic->set_reg_79();
4245	d_rfic->set_reg_80();
4246	d_rfic->set_reg_81();
4247	d_rfic->set_reg_82();
4248	d_rfic->set_reg_83();
4249	d_rfic->set_reg_84();
4250	d_rfic->set_reg_85();
4251	d_rfic->set_reg_86();
4252	d_rfic->set_reg_87();
4253	d_rfic->set_reg_88();
4254	d_rfic->set_reg_89();
4255	d_rfic->set_reg_90();
4256	d_rfic->set_reg_91();
4257	d_rfic->set_reg_96();
4258	d_rfic->set_reg_97();
4259	d_rfic->set_reg_98();
4260	d_rfic->set_reg_99();
4261	d_rfic->set_reg_104();
4262	d_rfic->set_reg_105();
4263	d_rfic->set_reg_106();
4264	d_rfic->set_reg_107();
4265	d_rfic->set_reg_108();
4266	d_rfic->set_reg_109();
4267	d_rfic->set_reg_110();
4268	d_rfic->set_reg_111();
4269	d_rfic->set_reg_112();
4270	d_rfic->set_reg_113();
4271	d_rfic->set_reg_114();
4272	d_rfic->set_reg_116();
4273	d_rfic->set_reg_117();
4274	d_rfic->set_reg_118();
4275	d_rfic->set_reg_119();
4276	d_rfic->set_reg_120();
4277	d_rfic->set_reg_121();
4278	d_rfic->set_reg_122();
4279	d_rfic->set_reg_123();
4280	d_rfic->set_reg_124();
4281	d_rfic->set_reg_125();
4282	d_rfic->set_reg_126();
4283	d_rfic->set_reg_127();
4284	d_rfic->set_reg_128();
4285	d_rfic->set_reg_133();
4286	d_rfic->set_reg_134();
4287	d_rfic->set_reg_135();
4288	d_rfic->set_reg_136();
4289	d_rfic->set_reg_137();
4290	d_rfic->set_reg_138();
4291	d_rfic->set_reg_139();
4292	d_rfic->set_reg_140();
4293	d_rfic->set_reg_141();
4294	d_rfic->set_reg_142();
4295	d_rfic->set_reg_143();
4296	d_rfic->set_reg_144();
4297	d_rfic->set_reg_145();
4298	d_rfic->set_reg_146();
4299	d_rfic->set_reg_147();
4300	d_rfic->set_reg_152();
4301	d_rfic->set_reg_153();
4302	d_rfic->set_reg_192();
4303	d_rfic->set_reg_193();
4304	d_rfic->set_reg_194();
4305	d_rfic->set_reg_195();
4306	d_rfic->set_reg_196();
4307	d_rfic->set_reg_197();
4308	d_rfic->set_reg_198();
4309	d_rfic->set_reg_199();
4310	d_rfic->set_reg_200();
4311	d_rfic->set_reg_201();
4312	d_rfic->set_reg_202();
4313	d_rfic->set_reg_203();
4314	d_rfic->set_reg_204();
4315	d_rfic->set_reg_205();
4316	d_rfic->set_reg_206();
4317	d_rfic->set_reg_207();
4318
4319	// Get digital block out of digital reset state
4320	d_rfic->Rst_n_async_3 = 1;
4321	d_rfic->set_reg_128();
4322
4323	// Set RX LNA port to LNA1 (SGO non-chopping mixer)
4324	// FIXME
4325	//d_rfic->rx_lna = 1;
4326	d_rfic->rx_lna = 5;
4327
4328	// Set LNA bias
4329	d_rfic->rx_lnab = 1;
4330
4331	// Enable LO clock to mixer
4332	d_rfic->rx_rxchen = 1;
4333
4334	d_rfic->set_reg_205();
4335
4336	// Enable RX Filter
4337	d_rfic->rx_fen = 1;
4338
4339	// Enable baseband filter chopper clock
4340	d_rfic->rx_chcken = 1;
4341
4342	// Enable chopper clock to all mixers
4343	d_rfic->rx_cen = 7;
4344
4345	// Set chopper divide setting
4346	// FIXME
4347	//d_rfic->rx_chck = 0
4348	d_rfic->rx_chck = 1;
4349
4350	d_rfic->set_reg_195();
4351
4352	// Enable filter output
4353	d_rfic->rx_foe = 1;
4354
4355	// Enable on-channel detector
4356	//d_rfic->rx_onchen = 1
4357
4358	// Enable off-channel detector
4359	//d_rfic->rx_offchen = 1
4360
4361
4362	d_rfic->set_reg_196();
4363
4364	// Set BQ filter Q to 1.33
4365	d_rfic->rx_qs = 2;
4366
4367	// Set BQ resistor value to 1.4 kohms
4368	d_rfic->rx_rq = 0;
4369
4370	d_rfic->set_reg_198();
4371
4372	// Set VGA resistor value to 2.5 kohms
4373	d_rfic->rx_rv = 0;
4374
4375	// Set PMA Rf resistor to 5 kohms
4376	d_rfic->rx_rfp = 00;
4377
4378	d_rfic->set_reg_199();
4379
4380	// Set compensation control
4381	d_rfic->rx_cc_2to0 = 0;
4382
4383	d_rfic->set_reg_203();
4384
4385	// Enable DCOC DAC
4386	d_rfic->rx_den = 1;
4387
4388	d_rfic->set_reg_192();
4389
4390	// Enable DCOC comparator
4391	d_rfic->rx_cmpen = 1;
4392
4393	d_rfic->set_reg_193();
4394
4395	// RC Tune enable
4396	// FIXME
4397	//d_rfic->rx_ten = 1;
4398	d_rfic->rx_ten = 0;
4399
4400	// RC Tune ramp circuit enable
4401	// FIXME
4402	//d_rfic->rx_ren = 1;
4403	d_rfic->rx_ren = 0;
4404
4405	// Select DCOC/RC Tune divider, divide by 8
4406	d_rfic->rx_dv = 3;
4407
4408	d_rfic->set_reg_194();
4409
4410	// Enable DCOC
4411	d_rfic->rx_dcoc = 1;
4412
4413	d_rfic->set_reg_193();
4414
4415	// POR On. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
4416	d_rfic->Clk_driver_en_3 = 1;
4417
4418	// POR On
4419	d_rfic->qu_reg_en_3 = 1;
4420
4421	// POR On
4422	d_rfic->qq_reg_en_3 = 1;
4423	// POR Off
4424	d_rfic->win_rst_3 = 0;
4425
4426	// POR On
4427	d_rfic->fineEn_3 = 0 ;
4428
4429	// POR Off
4430	d_rfic->fineEnb_3 = 1;
4431
4432	// POR Off
4433	//d_rfic->rsffEn_3 = 0;
4434
4435	// POR On
4436	d_rfic->dl_en_3 = 1;
4437
4438	// POR On
4439	d_rfic->cp_en_3 = 1;
4440
4441	d_rfic->set_reg_124();
4442	d_rfic->set_reg_125();
4443	}
4444
4445	db_rfic_rx::~db_rfic_rx()
4446	{
4447	// std::cout << "inside db_rfic_rx destructor "<< std::endl;
4448	// Power down
4449
4450	// Set RX LNA path (off)
4451	d_rfic->rx_lna = 0;
4452
4453	// Disable LO clock to mixer
4454	d_rfic->rx_rxchen = 0;
4455
4456	d_rfic->set_reg_205();
4457	// Disable RX Filter
4458	d_rfic->rx_fen = 0;
4459
4460	// Disable baseband filter chipper clock
4461	d_rfic->rx_chcken = 0;
4462
4463	// Disable chopper clock to all mixers
4464	d_rfic->rx_cen = 0;
4465	d_rfic->set_reg_195();
4466
4467	// Disable filter output
4468	d_rfic->rx_foe = 0;
4469
4470	// Disable on-channel detector
4471	d_rfic->rx_onchen = 0;
4472
4473	// Disable off-channel detector
4474	d_rfic->rx_offchen = 0;
4475
4476	d_rfic->set_reg_196();
4477
4478	// Disable DCOC DAC
4479	d_rfic->rx_den = 0;
4480
4481	d_rfic->set_reg_192();
4482
4483	// Disable DCOC comparator
4484	d_rfic->rx_cmpen = 0;
4485
4486	d_rfic->set_reg_193();
4487
4488	// RC Tune disable
4489	d_rfic->rx_ten = 0;
4490
4491	// RC Tune ramp circuit disable
4492	d_rfic->rx_ren = 0;
4493
4494	d_rfic->set_reg_194();
4495
4496	// Disable DCOC
4497	d_rfic->rx_dcoc = 0;
4498
4499	d_rfic->set_reg_193();
4500
4501	// POR Off. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
4502	d_rfic->Clk_driver_en_3 = 0;
4503
4504	// POR Off
4505	d_rfic->qu_reg_en_3 = 0;
4506
4507	// POR Off
4508	d_rfic->qq_reg_en_3 = 0;
4509
4510	// POR Off
4511	d_rfic->win_rst_3 = 0;
4512
4513	// POR Off
4514	d_rfic->fineEn_3 = 0;
4515
4516	// POR Off
4517	d_rfic->fineEnb_3 = 0;
4518
4519	// POR Off
4520	//d_rfic->rsffEn_3 = 0;
4521
4522	// POR Off
4523	d_rfic->dl_en_3 = 0;
4524
4525	// POR Off
4526	d_rfic->cp_en_3 = 0;
4527
4528	d_rfic->set_reg_124();
4529	d_rfic->set_reg_125();
4530
4531	// Put digital block into digital reset state
4532	d_rfic->Rst_n_async_3 = 0;
4533	d_rfic->set_reg_58();
4534	shutdown();
4535
4536
4537	}
4538
4539	void
4540	db_rfic_rx::shutdown()
4541	{
4542	if (!d_is_shutdown){
4543	d_is_shutdown = true;
4544	shutdown_common();
4545	}
4546	}
4547
4548	bool
4549	db_rfic_rx::select_rx_antenna(std::string which_antenna){
4550	//
4551	//Specif(y which antenna port to use for transmission.
4552	//@param which_antenna: either LNA1/0, LNA2/1, LNA3/2, LNA4/3 or MIX5/4
4553	//
4554	//std::cout<<"inside select rx antenna..antenna used is :"<<which_antenna
4555	which_antenna = "MIX5";
4556	if( which_antenna == "LNA1"){
4557	d_rfic->rx_lna = 1;
4558	d_rfic->set_reg_205();
4559	}
4560	else if( which_antenna == "LNA2"){
4561	d_rfic->rx_lna = 2;
4562	d_rfic->set_reg_205();
4563	}
4564	else if( which_antenna == "LNA3"){
4565	d_rfic->rx_lna = 3;
4566	d_rfic->set_reg_205();
4567	}
4568	else if( which_antenna == "LNA4"){
4569	d_rfic->rx_lna = 4;
4570	d_rfic->set_reg_205();
4571	}
4572	else if( which_antenna == "MIX5"){
4573	d_rfic->rx_lna = 5;
4574	d_rfic->set_reg_205();
4575	}
4576	else{
4577	std::cout<< "FJAHFJDH which_antenna must be either LNA1/0, LNA2/1, LNA3/2, LNA4/3 or MIX5/4"<<std::endl;
4578	return false;
4579	}
4580
4581	return true;
4582	}
4583
4584	bool
4585	db_rfic_rx::select_rx_antenna(int which_antenna){
4586	//
4587	//Specif(y which antenna port to use for transmission.
4588	//@param which_antenna: either 'rx1', 'rx2' or 'rx3'
4589	//
4590	if( which_antenna == 0){
4591	d_rfic->rx_lna = 1;
4592	d_rfic->set_reg_205();
4593	}
4594	else if( which_antenna == 1){
4595	d_rfic->rx_lna = 2;
4596	d_rfic->set_reg_205();
4597	}
4598	else if( which_antenna == 2){
4599	d_rfic->rx_lna = 3;
4600	d_rfic->set_reg_205();
4601	}
4602	else if( which_antenna == 3){
4603	d_rfic->rx_lna = 4;
4604	d_rfic->set_reg_205();
4605	}
4606	else if( which_antenna == 4){
4607	d_rfic->rx_lna = 5;
4608	d_rfic->set_reg_205();
4609	}
4610	else{
4611	std::cout<< "which_antenna must be either LNA1/0, LNA2/1, LNA3/2, LNA4/3 or MIX5/4"<<std::endl;
4612	return false;
4613	}
4614	return true;
4615	}
4616
4617	float
4618	db_rfic_rx::gain_min()
4619	{
4620	return 0.0;
4621	}
4622
4623	float
4624	db_rfic_rx::gain_max()
4625	{
4626	return 40.0;
4627	}
4628
4629
4630	bool
4631	db_rfic_rx::set_gain(float gain)
4632	{
4633	return d_rfic->set_rx_gain(gain);
4634	}
4635
4636	struct freq_result_t
4637	db_rfic_rx::set_freq(double target_frequency)
4638	{
4639	return d_rfic->set_rx_freq(target_frequency);
4640	}
4641
4642	bool
4643	db_rfic_rx::set_phase(int phase)
4644	{
4645	return d_rfic->set_rx_phase(phase);
4646	}
4647
4648	bool
4649	db_rfic_rx::set_bw(float bw)
4650	{
4651	return d_rfic->set_rx_bw(bw);
4652	}
4653
4654	void
4655	db_rfic_rx::enable_fb(){
4656	// Enable transmitter feedback to receiver for DC offset, etc.
4657	d_rfic->enable_tx_fb();
4658	}
4659
4660	void
4661	db_rfic_rx::disable_tx_fb(){
4662	// Disable transmitter feedback to receiver
4663	return d_rfic->disable_tx_fb();
4664	}
4665	float
4666	db_rfic_rx::fb_gain_min(){
4667	return 0.0;
4668	}
4669
4670	float
4671	db_rfic_rx::fb_gain_max(){
4672	return 40.0;
4673	}
4674
4675	void
4676	db_rfic_rx::set_fb_gain(float gain){
4677	// Set feedback gain, in dB
4678	d_rfic->set_fb_gain(gain);
4679	}
4680
4681	bool
4682	db_rfic_rx::set_fb_freq(double target_freq){
4683	// Set feedback frequency, in Hz
4684	return d_rfic->set_fb_freq(target_freq);
4685	}
4686
4687	bool
4688	db_rfic_rx::set_fb_phase(int phase){
4689	// Set feedback phase offset, in degrees
4690	return d_rfic->set_fb_phase(phase);
4691	}
4692
4693	void
4694	db_rfic_rx::set_fb_bw(float bw){
4695	// Set feedback bandwidth, in Hz
4696	d_rfic->set_fb_bw(bw);
4697	}
4698
4699	int
4700	db_rfic_rx::RSSI_fade(){
4701	// Get received signal strength indicators
4702	// Returns fade
4703	// Fade is proportional to how often the signal is low
4704	return d_rfic->RSSI_fade();
4705	}
4706
4707	int
4708	db_rfic_rx::RSSI_clip(){
4709	// Get received signal strength indicators
4710	// Returns clip
4711	// Clip is proportional to how often the signal is high
4712	return d_rfic->RSSI_clip();
4713	}
4714
4715	float
4716	db_rfic_rx::gain_db_per_step()
4717	{
4718	return d_rfic->usrp()->pga_db_per_step();
4719	}
4720
4721	#endif
4722
4723

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