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db_rfic.cc @ 480

Revision 480, 130.6 KB (checked in by trnewman, 15 years ago)
Adding motorola rfic driver files

Line
1	#ifndef DB_RFIC_H
2	#define DB_RFIC_H
3	#include <db_rfic.h>
4	#include <db_base_impl.h>
5	#include <cmath>
6	#include <boost/thread.hpp>
7	#include <boost/weak_ptr.hpp>
8
9	int TX_EN = (1<<6);
10
11	struct rfic_key {
12	std::string serial_no;
13	int which;
14
15	bool operator==(const rfic_key &x){
16	return x.serial_no ==serial_no && x.which == which;
17	}
18	};
19
20	class rfic{
21
22	public:
23	usrp_basic *d_raw_usrp;
24	int d_which;
25	bool d_is_shutdown;
26	int d_spi_format, d_spi_enable,d_spi_format_no_header;
27	int Ngt3, NorNdiv4, RorFrNpRdiv4_25to18, RorFrNpRdiv4_17to10, RorFrNpRdiv4_9to2, RorFrNpRdiv4_1to0, Qu_tx_Ngt3 \
28	,NorNdiv4_phsh, RorFrNpRdiv4_phsh_25to18, RorFrNpRdiv4_phsh_17to10, RorFrNpRdiv4_phsh_9to2, \
29	RorFrNpRdiv4_phsh_1to0, Passthru_ref_clk, Byp_ram, Dis_adr_dith, Dis_p5G_dith, Byp_fine, Exclude32, Dis_risedge \
30	, Dis_faledge, Spr_puls_en, Spr_puls_val_a_9to3, Spr_pulse_val_2to0, Spr_puls_val_b_9to2, Spr_puls_val_b_1to0 \
31	,Thru_ris_en, Thru_ris_tap_11to6, Thru_ris_tap_5to0, Thru_fal_en, Thru_fal_tap_11to6, Thru_fal_tap_5to0, \
32	Dig_delay, Clk_driver_en, qu_reg_en, qq_reg_en, win_rst, fineEn, fineEnb, rsffEn, dl_en, cp_en, forceCpUpb, \
33	forceCpDn, pdUpTune_1to0, pdDnTune_1to0, cpUpTune_2to0, cpDnTune_2to0, pdEn, digClkPhase_7to0, Rst_n_async;
34
35	std::string L1_lup00_15to8; //Read-only//
36	std::string L1_lup90_15to8; //Read-only//
37	std::string Merg_ris_fin; //Read-only//
38	std::string Merg_fal_fin; //Read-only//
39
40	int Qg00degDelay_0to4 ,Qg90degDelay_0to4, Qg180degDelay_0to4, Qg270degDelay_0to4, DischargeTap16_0to3, \
41	ChargeTap16_0to3, DischargeTapn_0to3, ChargeTapn16_0to3, X1sel_32to39, X1sel_40to47,X2sel_32to36, X2sel_37to41 \
42	,X4sel_32to36, X4sel_37to41, X8sel_32to36, X8sel_41, X8sel_37to40, qutx_fwd_180Cal_en, qutx_fwd_0Cal_en;
43	//-------------------------------------------------------------------------------------------------------
44	// TRANSMIT FEEDBACK QuIET FREQUENCY GENERATOR
45	//-------------------------------------------------------------------------------------------------------
46	int Ngt3_2, NorNdiv4_2, RorFrNpRdiv4_25to18_2, RorFrNpRdiv4_17to10_2, RorFrNpRdiv4_9to2_2, RorFrNpRdiv4_1to0_2, \
47	Qu_tx_Ngt3_2, NorNdiv4_phsh_2, RorFrNpRdiv4_phsh_25to18_2, RorFrNpRdiv4_phsh_17to10_2, RorFrNpRdiv4_phsh_9to2_2, \
48	RorFrNpRdiv4_phsh_1to0_2, Passthru_ref_clk_2, Byp_ram_2, Dis_adr_dith_2, Dis_p5G_dith_2, Byp_fine_2, \
49	Exclude32_2, Dis_risedge_2, Dis_faledge_2, Spr_puls_en_2, Spr_puls_val_a_9to3_2, Spr_pulse_val_2to0_2, \
50	Spr_puls_val_b_9to2_2, Spr_puls_val_b_1to0_2, Thru_ris_en_2, Thru_ris_tap_11to6_2, Thru_ris_tap_5to0_2, \
51	Thru_fal_en_2, Thru_fal_tap_11to6_2, Thru_fal_tap_5to0_2, Dig_delay_2, Clk_driver_en_2, qu_reg_en_2, \
52	qq_reg_en_2, win_rst_2 , fineEn_2, fineEnb_2, rsffEn_2, dl_en_2, cp_en_2, forceCpUpb_2, forceCpDn_2, \
53	pdUpTune_1to0_2, pdDnTune_1to0_2, cpUpTune_2to0_2, cpDnTune_2to0_2, pdEn_2 , digClkPhase_7to0_2, Rst_n_async_2;
54
55	std::string L1_lup00_15to8_2; //Read-only//
56	std::string L1_lup90_15to8_2; //Read-only//
57	std::string Merg_ris_fin_2; //Read-only//
58	std::string Merg_fal_fin_2; //Read-only//
59	std::string Decod_in_0deg;
60	std::string L1_lup00_15to8_3;
61	std::string L1_lup90_15to8_3;
62	std::string Merg_ris_fin_3;
63	std::string Merg_fal_fin_3;
64
65
66	int Qg00degDelay_0to4_2, Qg90degDelay_0to4_2, Qg180degDelay_0to4_2, Qg270degDelay_0to4_2, DischargeTap16_3to0;
67
68
69	int ChargeTap16_3to0, DischargeTapn_3to0 , ChargeTapn16_3to0, X1sel_32to39_2;
70	int X1sel_40to47_2, X2sel_32to36_2, X2sel_37to41_2, X4sel_32to36_2, X4sel_37to41_2, X8sel_32to36_2, X8sel_41_2;
71	int X8sel_37to40_2, qutx_fb_180Cal_en, qutx_fb_0Cal_en, qutx_fb_180Rsff_en, qutx_fb_0Rsff_en, N, R_11to8;
72	int R_7to0, Asyncrst_n, Cp_sel_6to0, Cp_sel_8to7, ForceFout, ForceFoutb, Out_en, Dll_en, Ana_en, Ngt3_3;
73	int NorNdiv4_3, RorFrNpRdiv4_25to18_3, RorFrNpRdiv4_17to10_3, RorFrNpRdiv4_9to2_3, RorFrNpRdiv4_1to0_3;
74	int Qu_tx_Ngt3_3, NorNdiv4_phsh_3, RorFrNpRdiv4_phsh_25to18_3, RorFrNpRdiv4_phsh_17to10_3, RorFrNpRdiv4_phsh_9to2_3;
75	int RorFrNpRdiv4_phsh_1to0_3, Passthru_ref_clk_3, Byp_ram_3, Dis_adr_dith_3, Dis_p5G_dith_3, Byp_fine_3;
76	int Exclude32_3, Dis_risedge_3, Dis_faledge_3, Spr_puls_en_3, Spr_puls_val_a_9to3_3, Spr_pulse_val_2to0_3;
77	int Spr_puls_val_b_9to2_3, Spr_puls_val_b_1to0_3, Thru_ris_en_3, Thru_ris_tap_11to6_3, Thru_ris_tap_5to0_3;
78	int Thru_fal_en_3, Thru_fal_tap_11to6_3, Thru_fal_tap_5to0_3, Dig_delay_3, Clk_driver_en_3, qu_reg_en_3;
79	int qq_reg_en_3, win_rst_3, fineEn_3, fineEnb_3, rsffEn_3, dl_en_3, cp_en_3, forceCpUpb_3, forceCpDn_3;
80	int pdUpTune_1to0_3, pdDnTune_1to0_3, cpUpTune_2to0_3, cpDnTune_2to0_3, pdEn_3, digClkPhase_7to0_3, Rst_n_async_3;
81	int Qg00degDelay_0to4_3, Qg90degDelay_0to4_3, Qg180degDelay_0to4_3, Qg270degDelay_0to4_3, DischargeTap16_0to3_3;
82	int ChargeTap16_0to3_3, DischargeTapn_0to3_3, ChargeTapn16_0to3_3, X1sel_32to39_3, X1sel_40to47_3, X2sel_32to36_3;
83	int X2sel_37to41_3, X4sel_32to36_3, X4sel_37to41_3, X8sel_32to36_3, X8sel_41_3, X8sel_37to40_3, qurx_180Cal_en;
84	int qurx_0Cal_en, extClkEn, extClkEnBNOTD7, div2_rst, TxChClkSel, TxChClkEn, tx_bb_en, tx_bb_fdbk_bw;
85	int tx_bb_fdbk_cal_en, tx_bb_fdbk_cart_err_en, tx_bb_fdbk_cart_fb_en, tx_bb_fdbk_cart_fwd_en, tx_bb_fdbk_en;
86	int tx_bb_fdbk_1q_sel, tx_bb_fdbk_lp, tx_bb_fdbk_statt, tx_bb_fdbk_swapi, tx_bb_fdbk_swapq, tx_bb_gain_cmp;
87	int tx_bb_lp, tx_bb_swapi, tx_bb_swapq, tx_butt_bw, tx_bw_trck, tx_cart_en, tx_cart_fb_bb_statt;
88	int tx_cart_fb_dcoc_dac_I1, tx_cart_fb_dcoc_dac_I2, tx_cart_fb_dcoc_dac_Q1, tx_cart_fb_dcoc_dac_Q2;
89	int CartesianFeedbackpathDCOCenable, CartesianFeedbackpathenable, CartesianFBpathHiResolutionDCOCenable;
90	int CartesianFBpathBW, CartesianFBRFGain, CartesianFBpathSwapIandIx, CartesianFBpathSwapQandQx;
91	int CartesianFBpathSwitchtoforwardSummer, tx_cart_fb_lo_select, CartesianFBpathAmp1Gain, CartesianFBpathAmp2Gain;
92	int CartesianFBpathAmp3Gain, CartesianFBpathAmp4Gain, CartesianFBpathAmpCurrentSelect, CartesianFBpathZeroEnable;
93	int tx_cart_zero_statt, tx_inbuf_bw, tx_inbuf_statt, tx_output_channel_sel, tx_p1_bw, tx_pw_bw1, tx_p2_bw2; int PushPullBufferCurrent, tx_rf_aoc_bw, RFForwardPathEnable_toMUX, RFForwardPathEnable_ExternalPinenable;
94	int tx_rf_fwd_lp, tx_rf_fwd_statt1, tx_rf_fwd_statt2, BBQDivideby2or4Select, BBQQuadGenEnable;
95	int BBQPolyphaseQuadGenEnable, lofb_tun_s, lofb_tun_sx, lofw_tun_s2, lofw_tun_sx2, reserve_tx26, reserve_tx27;
96	int rx_Idac, rx_dcs, rx_den, rx_Qdac, rx_cmpen, rx_dcoc, rx_ten, rx_ren, rx_dven, rx_dv, rx_extc, rx_cen;
97	int rx_chck, rx_chcken, rx_fen, rx_onchen, rx_offchen, rx_foe, rx_offch, rx_onchf, rx_onchc, rx_qs, rx_bqg;
98	int rx_rq, rx_rv, rx_rip, rx_rfp, rx_cp_12to8, rx_gs, rx_cp_7to0, rx_cv_10to3, rx_cv_2to0, rx_cc_2to0;
99	int rx_cq_9to8, rx_cq_7to0, rx_lna, rx_lnab, rx_rxchen, rx_bbq_div2or4, rx_Loselect, poly_en, lorx_tun_s, lorx_tun_sx;
100
101	std::string rx_Icmpo; //I path DCOC comparator output. Output of the DCOC comparator - used for test purposes. Output only.//
102	std::string rx_Iodac; //I path DCOC DAC output. Output of the DCOC DACs - used to read result of DCOC correction circuitry. Output only.//
103	std::string rx_Qcmpo; //Q path DCOC comparator output. Output of the DCOC comparator - used for test purposes. Output only.//
104	std::string rx_Qodac; //Q path DCOC DAC output. Output of the DCOC DACs - used to read result of DCOC correction circuitry. Output only.//
105	std::string rx_rc;
106
107	int shft_cml_in, vagenable1, vagenable2, TestMuxBufferEnable, TestMuxEnable, TestMuxSetting, txgain;
108
109	float Foutrx,Fclk,Fouttx, Foutrxb, Foutfb;
110
111	int Rst_n_async2,Rst_n_async3; //generated inside function in python code..have to be declared in c++
112	// Initialize GPIO and ATR
113	// GPIO are the general-purpose IO pins on the daughterboard
114	// IO_RX_06 must be used for ATR (1 = TX, 0 = RX)
115	// ATR is the automatic transmit/receive switching, done in the FPGA
116	// FIXME
117
118
119
120
121	usrp_basic *usrp(){
122	return d_raw_usrp;
123	}
124
125	rfic(usrp_basic_sptr usrp, int which);
126	~rfic();
127
128	bool rx_write_io(int, int); //the defination may need to be changed..mask should be a hex value...will rework this
129	bool rx_write_oe(int,int);
130	bool rx_set_atr_rxval(int);
131	bool rx_set_atr_txval(int);
132	bool rx_set_atr_mask(int);
133
134
135	void shutdown();
136	void send_reg(int,int);
137
138	//send register wrapper function difinations//
139	void set_reg_0();
140	void set_reg_1();
141	void set_reg_2();
142	void set_reg_3();
143	void set_reg_4();
144	void set_reg_5();
145	void set_reg_6();
146	void set_reg_7();
147	void set_reg_8();
148	void set_reg_9();
149	void set_reg_10();
150	void set_reg_12();
151	void set_reg_13();
152	void set_reg_14();
153	void set_reg_15();
154	void set_reg_16();
155	void set_reg_17();
156	void set_reg_18();
157	void set_reg_19();
158	void set_reg_20();
159	void set_reg_21();
160	void set_reg_22();
161	void set_reg_23();
162	void set_reg_24();
163	void set_reg_29();
164	void set_reg_30();
165	void set_reg_31();
166	void set_reg_32();
167	void set_reg_33();
168	void set_reg_34();
169	void set_reg_35();
170	void set_reg_36();
171	void set_reg_37();
172	void set_reg_38();
173	void set_reg_39();
174	void set_reg_40();
175	void set_reg_41();
176	void set_reg_42();
177	void set_reg_43();
178	void set_reg_48();
179	void set_reg_49();
180	void set_reg_50();
181	void set_reg_51();
182	void set_reg_52();
183	void set_reg_53();
184	void set_reg_54();
185	void set_reg_55();
186	void set_reg_56();
187	void set_reg_57();
188	void set_reg_58();
189	void set_reg_60();
190	void set_reg_61();
191	void set_reg_62();
192	void set_reg_63();
193	void set_reg_64();
194	void set_reg_65();
195	void set_reg_66();
196	void set_reg_67();
197	void set_reg_68();
198	void set_reg_69();
199	void set_reg_70();
200	void set_reg_71();
201	void set_reg_72();
202	void set_reg_77();
203	void set_reg_78();
204	void set_reg_79();
205	void set_reg_80();
206	void set_reg_81();
207	void set_reg_82();
208	void set_reg_83();
209	void set_reg_84();
210	void set_reg_85();
211	void set_reg_86();
212	void set_reg_87();
213	void set_reg_88();
214	void set_reg_89();
215	void set_reg_90();
216	void set_reg_91();
217	void set_reg_96();
218	void set_reg_97();
219	void set_reg_98();
220	void set_reg_99();
221	void set_reg_104();
222	void set_reg_105();
223	void set_reg_106();
224	void set_reg_107();
225	void set_reg_108();
226	void set_reg_109();
227	void set_reg_110();
228	void set_reg_111();
229	void set_reg_112();
230	void set_reg_113();
231	void set_reg_114();
232	void set_reg_116();
233	void set_reg_117();
234	void set_reg_118();
235	void set_reg_119();
236	void set_reg_120();
237	void set_reg_121();
238	void set_reg_122();
239	void set_reg_123();
240	void set_reg_124();
241	void set_reg_125();
242	void set_reg_126();
243	void set_reg_127();
244	void set_reg_128();
245	void set_reg_133();
246	void set_reg_134();
247	void set_reg_135();
248	void set_reg_136();
249	void set_reg_137();
250	void set_reg_138();
251	void set_reg_139();
252	void set_reg_140();
253	void set_reg_141();
254	void set_reg_142();
255	void set_reg_143();
256	void set_reg_144();
257	void set_reg_145();
258	void set_reg_146();
259	void set_reg_147();
260	void set_reg_152();
261	void set_reg_153();
262	void set_reg_156();
263	void set_reg_157();
264	void set_reg_158();
265	void set_reg_159();
266	void set_reg_160();
267	void set_reg_161();
268	void set_reg_162();
269	void set_reg_163();
270	void set_reg_164();
271	void set_reg_165();
272	void set_reg_166();
273	void set_reg_167();
274	void set_reg_168();
275	void set_reg_169();
276	void set_reg_170();
277	void set_reg_171();
278	void set_reg_172();
279	void set_reg_173();
280	void set_reg_174();
281	void set_reg_175();
282	void set_reg_176();
283	void set_reg_177();
284	void set_reg_178();
285	void set_reg_179();
286	void set_reg_180();
287	void set_reg_181();
288	void set_reg_192();
289	void set_reg_193();
290	void set_reg_194();
291	void set_reg_195();
292	void set_reg_196();
293	void set_reg_197();
294	void set_reg_198();
295	void set_reg_199();
296	void set_reg_200();
297	void set_reg_201();
298	void set_reg_202();
299	void set_reg_203();
300	void set_reg_204();
301	void set_reg_205();
302	void set_reg_206();
303	void set_reg_207();
304	void set_reg_220();
305	void set_reg_222();
306	//
307
308	void read_reg_25();
309	void read_reg_26();
310	void read_reg_27();
311	void read_reg_28();
312	void read_reg_73();
313	void read_reg_74();
314	void read_reg_75();
315	void read_reg_76();
316	void read_reg_100();
317	void read_reg_125();
318	void read_reg_129();
319	void read_reg_130();
320	void read_reg_131();
321	void read_reg_132();
322	void read_reg_208();
323	void read_reg_209();
324	void read_reg_210();
325
326	char get_reg(int);
327	bool set_rx_gain(float);
328	bool set_tx_gain(float);
329	void set_fb_gain(float);
330	int* calc_freq_vars(double,double);
331	int* calc_phase_vars(double,double,double);
332	struct freq_result_t set_rx_freq(double);
333	struct freq_result_t set_tx_freq(double);
334	bool set_fb_freq(double);
335
336	bool set_rx_phase(int);
337	bool set_tx_phase(int);
338
339	bool set_fb_phase(int);
340	bool set_rx_bw(float);
341	bool set_tx_bw(float);
342	void set_fb_bw(float);
343	void enable_tx_fb();
344	void disable_tx_fb();
345	int RSSI_fade();
346	int RSSI_clip();
347
348	};
349
350
351	/***************************method definitions***************************/
352
353	rfic::rfic(usrp_basic_sptr _usrp, int which)
354	: d_raw_usrp(_usrp.get()), d_which(which)
355	{
356	Ngt3 = 0; //Output frequency control bit. Calculated.//
357	NorNdiv4 = 1; //Output frequency control word. Calculated.//
358	RorFrNpRdiv4_25to18 = 0; //Output frequency control word. Calculated//
359	RorFrNpRdiv4_17to10 = 0; ////
360	RorFrNpRdiv4_9to2 = 0; ////
361	RorFrNpRdiv4_1to0 = 0; ////
362	Qu_tx_Ngt3 = 0; //Enables divide-by-4 freq divider - Phase shift control bit. Calculated//
363	NorNdiv4_phsh = 1; //Phase shift control word. Calculated.//
364	RorFrNpRdiv4_phsh_25to18 = 0; //Phase shift control word. Calculated.//
365	RorFrNpRdiv4_phsh_17to10 = 0; ////
366	RorFrNpRdiv4_phsh_9to2 = 0; ////
367	RorFrNpRdiv4_phsh_1to0 = 0; ////
368	Passthru_ref_clk = 0; //A test mode where the 1 GHz input reference is passed directly to the output//
369	Byp_ram = 1; //Bypass the SRAMs//
370	Dis_adr_dith = 1; //Disable the dither generator in the ca2adr block//
371	Dis_p5G_dith = 1; //Disable the dither generator in the lup2decod block//
372	Byp_fine = 1; //Bypass fine delay line control bit//
373	Exclude32 = 0; //Bypass fine delay line control bit (exclude 32)//
374	Dis_risedge = 0; //Disable the rising edges decoders//
375	Dis_faledge = 0; //Disable the falling edges decoders//
376	Spr_puls_en = 0; //enable spur pulsing//
377	Spr_puls_val_a_9to3 = 0; //spur pulsing control word//
378	Spr_pulse_val_2to0 = 0; ////
379	Spr_puls_val_b_9to2 = 8; //spur pulsing control word//
380	Spr_puls_val_b_1to0 = 0 ;////
381	Thru_ris_en = 0; //Put rising edges decoders into through-tap mode//
382	Thru_ris_tap_11to6 = 32; //Through-tap control word//
383	Thru_ris_tap_5to0 = 0; ////
384	Thru_fal_en = 0; //Put falling edges decoders into through-tap mode//
385	Thru_fal_tap_11to6 = 32; //Through-tap control word//
386	Thru_fal_tap_5to0 = 0; ////
387	Dig_delay = 0; //This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control.//
388	Clk_driver_en = 0; //This allows the clock to reach the digital block. It first passes through the digital/analog clock synchronization mux, which means that dlEn must be on (dlEn=1) and Clk_driver=1 for the digital block to receive a clock. See Byp_fine, address 10, bit 6//
389	qu_reg_en = 0; //This bit enables the voltage regulators that supply 1.2 V to all the analog block functions. There are 6 separate regulators that are simultaneously enabled by this bit.//
390	qq_reg_en = 0; //This bit enables the voltage regulators that supply 1.2 V to all the Quad Gen functions. There are 3 separate regulators that are simultaneously enabled by this bit.//
391	win_rst = 0; //When this bit is high, the windowing function is in a reset state, which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block.//
392	fineEn = 0; //This bit, when high, routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS. When low, the coarse tap is routed directly to the output RS Flip Flop.//
393	fineEnb = 0; //Opposite of fineEn//
394	rsffEn = 0; //This bit must be high to send the QuIET 0 and 180 degree calibration signals off chip. It does not control the RS Flip Flop outputs of the DDS, though it may have some second order (coupling) effect.//
395	dl_en = 1; //Allows the PLL reference to enter the QuIET delay line when enabled.//
396	cp_en = 1; //This bit, when enables, activates the charge pump that controls the delay line via the single pole (one capacitor) DLL loop filter.//
397	forceCpUpb = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the pmos device connected to the DLL loop filter cap turns on and sources current into the cap, thereby increasing the delay line control voltage. //
398	forceCpDn = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the nmos device connected to the DLL loop filter cap turns off and allows the pmos device to charge up the loop cap as described above.//
399	pdUpTune_1to0 = 3; //These bits control the pulse width from the phase detector into the charge up port of the charge pump. 00 turns the charge up signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
400	pdDnTune_1to0 = 0; //These bits control the pulse width from the phase detector into the charge down port of the charge pump. 00 turns the charge down signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
401	cpUpTune_2to0 = 7; //These bits control amount of current that is sourced while the charge up signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
402	cpDnTune_2to0 = 2; //These bits control amount of current that is sinked while the charge down signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
403	pdEn = 1; //When enables, the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21. When disabled, the forceCpUp and forceCpDn settings will control the charge pump.//
404	digClkPhase_7to0 = 4; //Only one bit in this field should be active at one time. This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block. This is needed to control the windowing function of the DDS.//
405	Rst_n_async = 0; //Digital reset//
406
407	Qg00degDelay_0to4 = 31; //Adjusts series delay in the 0 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
408	Qg90degDelay_0to4 = 7; //Adjusts series delay in the 90 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
409	Qg180degDelay_0to4 = 31; //Adjusts series delay in the 180 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
410	Qg270degDelay_0to4 = 7; //Adjusts series delay in the 270 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
411	DischargeTap16_0to3 = 15; //Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
412	ChargeTap16_0to3 = 4; //Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
413	DischargeTapn_0to3 = 15; //Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
414	ChargeTapn16_0to3 = 2; //Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
415	X1sel_32to39 = 0; //Control for the divide-by-two and x1 functions.//
416	X1sel_40to47 = 0; //Control for the divide-by-two and x1 functions.//
417	X2sel_32to36 = 0; //Control for the x2 function.//
418	X2sel_37to41 = 0; //Control for the x2 function.//
419	X4sel_32to36 = 0; //Control for the x4 function.//
420	X4sel_37to41 = 0; //Control for the x4 function.//
421	X8sel_32to36 = 0; //Bit 41 is used for a fine line windowing control bit. If the fine line is needed, this bit needs to be set high if Fout is close to Fref (greater than ~ 950 MHz) or for some testing modes like pass through or thru_rise_en.//
422	X8sel_41 = 0; //hiFout - set for passthrough and Fout close to Fref//
423	X8sel_37to40 = 0; ////
424	qutx_fwd_180Cal_en = 0; //Enables the pad driver that sends the falling edge signal off chip. This falling edge signal is used internally to trigger the 'Reset' pin of the output RS Flip Flop.//
425	qutx_fwd_0Cal_en = 0; //Enables the pad driver that sends the rising edge signal off chip. This rising edge signal is used internally to trigger the 'Set' pin of the output RS Flip Flop.//
426	//-------------------------------------------------------------------------------------------------------
427	// TRANSMIT FEEDBACK QuIET FREQUENCY GENERATOR
428	//-------------------------------------------------------------------------------------------------------
429	Ngt3_2 = 0; //Output frequency control bit. Calculated.//
430	NorNdiv4_2 = 1; //Output frequency control word. Calculated.//
431	RorFrNpRdiv4_25to18_2 = 0; //Output frequency control word. Calculated.//
432	RorFrNpRdiv4_17to10_2 = 0; ////
433	RorFrNpRdiv4_9to2_2 = 0; ////
434	RorFrNpRdiv4_1to0_2 = 0; ////
435	Qu_tx_Ngt3_2 = 0; //Enables divide-by-4 freq divider - Phase shift control bit. Calculated//
436	NorNdiv4_phsh_2 = 1; //Phase shift control word. Calculated//
437	RorFrNpRdiv4_phsh_25to18_2 = 0; //Phase shift control word. Calculated//
438	RorFrNpRdiv4_phsh_17to10_2 = 0; ////
439	RorFrNpRdiv4_phsh_9to2_2 = 0; ////
440	RorFrNpRdiv4_phsh_1to0_2 = 0 ;////
441	Passthru_ref_clk_2 = 0; //Enable reference clock pass-through mode//
442	Byp_ram_2 = 1; //Bypass the SRAMs//
443	Dis_adr_dith_2 = 1; //Disable the dither generator in the ca2adr block//
444	Dis_p5G_dith_2 = 1; //Disable the dither generator in the lup2decod block//
445	Byp_fine_2 = 1; //Bypass fine delay line control bit//
446	Exclude32_2 = 0; //Bypass fine delay line control bit (exclude 32)//
447	Dis_risedge_2 = 0; //Disable the rising edges decoders//
448	Dis_faledge_2 = 0;//Disable the falling edges decoders//
449	Spr_puls_en_2 = 0; //Enable spur pulsing mode//
450	Spr_puls_val_a_9to3_2 = 0; //Spur pulsing mode control word//
451	Spr_pulse_val_2to0_2 = 0; ////
452	Spr_puls_val_b_9to2_2 = 8; //Spur pulsing mode control word//
453	Spr_puls_val_b_1to0_2 = 0 ;////
454	Thru_ris_en_2 = 0; //Put rising edges decoders into through-tap mode//
455	Thru_ris_tap_11to6_2 = 32; //Through-tap mode control word//
456	Thru_ris_tap_5to0_2 = 0; //Through-tap mode control word//
457	Thru_fal_en_2 = 0; //Put falling edges decoders into through-tap mode//
458	Thru_fal_tap_11to6_2 = 32; //Through-tap mode control word//
459	Thru_fal_tap_5to0_2 = 0; //Through-tap mode control word//
460	Dig_delay_2 = 0; //This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control.//
461	Clk_driver_en_2 = 0; //This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control. See Byp_fine, address 10, bit 6//
462	qu_reg_en_2 = 0; //This bit enables the voltage regulators that supply 1.2 V to all the analog block functions. There are 6 separate regulators that are simultaneously enabled by this bit.//
463	qq_reg_en_2 = 0; //This bit enables the voltage regulators that supply 1.2 V to all the Quad Gen functions. There are 3 separate regulators that are simultaneously enabled by this bit.//
464	win_rst_2 = 0; //When this bit is high, the windowing function is in a reset state, which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block.//
465	fineEn_2 = 0; //This bit, when high, routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS. When low, the coarse tap is routed directly to the output RS Flip Flop.//
466	fineEnb_2 = 0; //Opposite of fineEn.//
467	rsffEn_2 = 0; //This bit must be high to send the QuIET 0 and 180 degree calibration signals off chip. It does not control the RS Flip Flop outputs of the DDS, though it may have some second order (coupling) effect.//
468	dl_en_2 = 1; //Allows the PLL reference to enter the QuIET delay line when enabled.//
469	cp_en_2 = 1; //This bit, when enables, activates the charge pump that controls the delay line via the single pole (one capacitor) DLL loop filter.//
470	forceCpUpb_2 = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the pmos device connected to the DLL loop filter cap turns on and sources current into the cap, thereby increasing the delay line control voltage. //
471	forceCpDn_2 = 0; //This bit only matters when pdEn=0 (address 22, bit 1). When low, the nmos device connected to the DLL loop filter cap turns off and allows the pmos device to charge up the loop cap as described above.//
472	pdUpTune_1to0_2 = 3; //These bits control the pulse width from the phase detector into the charge up port of the charge pump. 00 turns the charge up signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
473	pdDnTune_1to0_2 = 0 ;//These bits control the pulse width from the phase detector into the charge down port of the charge pump. 00 turns the charge down signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
474	cpUpTune_2to0_2 = 7; //These bits control amount of current that is sourced while the charge up signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
475	cpDnTune_2to0_2 = 2; //These bits control amount of current that is sinked while the charge down signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
476	pdEn_2 = 1; //When enables, the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21. When disabled, the forceCpUp and forceCpDn settings will control the charge pump.//
477	digClkPhase_7to0_2 = 4; //Only one bit in this field should be active at one time. This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block. This is needed to control the windowing function of the DDS.//
478	Rst_n_async_2 = 0; //Digital reset//
479
480	Qg00degDelay_0to4_2 = 31; // Adjusts series delay in the 0 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
481	Qg90degDelay_0to4_2 = 7; // // Adjusts series delay in the 90 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.
482	Qg180degDelay_0to4_2 = 31; // Adjusts series delay in the 180 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
483	Qg270degDelay_0to4_2 = 7; // Adjusts series delay in the 270 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
484	DischargeTap16_3to0 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
485	ChargeTap16_3to0 = 4; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
486	DischargeTapn_3to0 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
487	ChargeTapn16_3to0 = 2; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
488	X1sel_32to39_2 = 0; // Control for the divide-by-two and x1 functions.//
489	X1sel_40to47_2 = 0 ;// Control for the divide-by-two and x1 functions.//
490	X2sel_32to36_2 = 0; // Control for the x2 function.//
491	X2sel_37to41_2 = 0; // Control for the x2 function.//
492	X4sel_32to36_2 = 0; // Control for the x4 function.//
493	X4sel_37to41_2 = 0; // Control for the x4 function.//
494	X8sel_32to36_2 = 0; // Bit 41 is used for a fine line windowing control bit. If the fine line is needed, this bit needs to be set high if Fout is close to Fref (greater than ~ 950 MHz) or for some testing modes like pass through or thru_rise_en.//
495	X8sel_41_2 = 0; // hiFout - set for passthrough and Fout close to Fref//
496	X8sel_37to40_2 = 0; // //
497	qutx_fb_180Cal_en = 0; // Enables the pad driver that sends the falling edge signal off chip. This falling edge signal is used internally to trigger the 'Reset' pin of the output RS Flip Flop.//
498	qutx_fb_0Cal_en = 0; // Enables the pad driver that sends the rising edge signal off chip. This rising edge signal is used internally to trigger the 'Set' pin of the output RS Flip Flop.//
499	qutx_fb_180Rsff_en = 0; // off//
500	qutx_fb_0Rsff_en = 0; // off//
501	// -------------------------------------------------------------------------------------------------------
502	// QuIET Dm
503	// -------------------------------------------------------------------------------------------------------
504	N = 4; // //
505	R_11to8 = 13; // //
506	R_7to0 = 172; // //
507	Asyncrst_n = 0; // off//
508	Cp_sel_6to0 = 63; // //
509	Cp_sel_8to7 = 0; // //
510	ForceFout = 0; // off//
511	ForceFoutb = 0; // off//
512	Out_en = 0; // off//
513	Dll_en = 1; // on//
514	Ana_en = 1; // off//
515
516	// -------------------------------------------------------------------------------------------------------
517	// RECEIVE QuIET FREQUENCY GENERATOR
518	// -------------------------------------------------------------------------------------------------------
519	Ngt3_3 = 0; // Output frequency control bit. Calculated.//
520	NorNdiv4_3 = 0; // Output frequency control word. Calculated.//
521	RorFrNpRdiv4_25to18_3 = 0; // Output frequency control word. Calculated.//
522	RorFrNpRdiv4_17to10_3 = 0; // //
523	RorFrNpRdiv4_9to2_3 = 0; // //
524	RorFrNpRdiv4_1to0_3 = 0; // //
525	Qu_tx_Ngt3_3 = 0; // Enables divide-by-4 freq divider - Phase shift control bit. Calculated.//
526	NorNdiv4_phsh_3 = 1; // Phase shift control word. Calculated//
527	RorFrNpRdiv4_phsh_25to18_3 = 0; // Phase shift control word. Calculated.//
528	RorFrNpRdiv4_phsh_17to10_3 = 0; // //
529	RorFrNpRdiv4_phsh_9to2_3 = 0; // //
530	RorFrNpRdiv4_phsh_1to0_3 = 0; // //
531	Passthru_ref_clk_3 = 0; // Enable reference clock pass-through mode//
532	Byp_ram_3 = 1; // Bypass the SRAMs//
533	Dis_adr_dith_3 = 1; // Disable the dither generator in the ca2adr block//
534	Dis_p5G_dith_3 = 1; // Disable the dither generator in the lup2decod block//
535	Byp_fine_3 = 1; // Bypass fine delay line control bit//
536	Exclude32_3 = 0; // Bypass fine delay line control bit (exclude 32)//
537	Dis_risedge_3 = 0; // Disable the rising edges decoders//
538	Dis_faledge_3 = 0; // Disable the falling edges decoders//
539	Spr_puls_en_3 = 0; // Enable spur pulsing mode//
540	Spr_puls_val_a_9to3_3 = 0; // Spur pulsing mode control word//
541	Spr_pulse_val_2to0_3 = 0; // //
542	Spr_puls_val_b_9to2_3 = 8; // Spur pulsing mode control word//
543	Spr_puls_val_b_1to0_3 = 0; // //
544	Thru_ris_en_3 = 0; // Put rising edges decoders into through-tap mode//
545	Thru_ris_tap_11to6_3 = 32; // Through-tap mode control word//
546	Thru_ris_tap_5to0_3 = 0; // Through-tap mode control word//
547	Thru_fal_en_3 = 0; // Put falling edges decoders into through-tap mode//
548	Thru_fal_tap_11to6_3 = 0; // Through-tap mode control word//
549	Thru_fal_tap_5to0_3 = 0; // Through-tap mode control word//
550	Dig_delay_3 = 0; // This bit provides delay to the clock going into the digital block. It is a remnant of past designs and should always be left offbecause the digClkPhase setting in address 23 provides much finer control.//
551	Clk_driver_en_3 = 0; // This allows the clock to reach the digital block. It first passes through the digital/analog clock synchronization mux, which means that dlEn must be on (dlEn=1) and Clk_driver=1 for the digital block to receive a clock. See Byp_fine, address 10, bit 6//
552	qu_reg_en_3 = 0; // This bit enables the voltage regulators that supply 1.2 V to all the analog block functions. There are 6 separate regulators that are simultaneously enabled by this bit.//
553	qq_reg_en_3 = 0; // This bit enables the voltage regulators that supply 1.2 V to all the Quad Gen functions. There are 3 separate regulators that are simultaneously enabled by this bit.//
554	win_rst_3 = 0; // When this bit is high, the windowing function is in a reset state, which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block.//
555	fineEn_3 = 0; // This bit, when high, routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS. When low, the coarse tap is routed directly to the output RS Flip Flop.//
556	fineEnb_3 = 0; // Opposite of fineEn.//
557	rsffEn_3 = 0; // This bit must be high to send the QuIET 0 and 180 degree calibration signals off chip. It does not control the RS Flip Flop outputs of the DDS, though it may have some second order (coupling) effect.//
558	dl_en_3 = 1; // Allows the PLL reference to enter the QuIET delay line when enabled.//
559	cp_en_3 = 1; // This bit, when enables, activates the charge pump that controls the delay line via the single pole (one capacitor) DLL loop filter.//
560	forceCpUpb_3 = 0; // This bit only matters when pdEn=0 (address 22, bit 1). When low, the pmos device connected to the DLL loop filter cap turns on and sources current into the cap, thereby increasing the delay line control voltage. //
561	forceCpDn_3 = 0; // This bit only matters when pdEn=0 (address 22, bit 1). When low, the nmos device connected to the DLL loop filter cap turns off and allows the pmos device to charge up the loop cap as described above.//
562	pdUpTune_1to0_3 = 3; // These bits control the pulse width from the phase detector into the charge up port of the charge pump. 00 turns the charge up signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
563	pdDnTune_1to0_3 = 1; // These bits control the pulse width from the phase detector into the charge down port of the charge pump. 00 turns the charge down signal off. 01 is the minimum pulse width setting and 11 is the maximum pulse width setting.//
564	cpUpTune_2to0_3 = 7; // These bits control amount of current that is sourced while the charge up signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
565	cpDnTune_2to0_3 = 2; // These bits control amount of current that is sinked while the charge down signal from the phase detector is high. 000 is minimum current and 111 is maximum current.//
566	pdEn_3 = 1; // When enables, the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21. When disabled, the forceCpUp and forceCpDn settings will control the charge pump.//
567	digClkPhase_7to0_3 = 4; // Only one bit in this field should be active at one time. This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block. This is needed to control the windowing function of the DDS.//
568	Rst_n_async_3 = 0; // Digital reset.//
569	Qg00degDelay_0to4_3 = 31; // Adjusts series delay in the 0 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
570	Qg90degDelay_0to4_3 = 31; // Adjusts series delay in the 90 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
571	Qg180degDelay_0to4_3 = 31; // Adjusts series delay in the 180 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
572	Qg270degDelay_0to4_3 = 31; // Adjusts series delay in the 270 degree path for the divide-by-two, x1, x2, and x4 quadrature generators.//
573	DischargeTap16_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
574	ChargeTap16_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
575	DischargeTapn_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps.//
576	ChargeTapn16_0to3_3 = 15; // Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps.//
577	X1sel_32to39_3 = 0; // Control for the divide-by-two and x1 functions.//
578	X1sel_40to47_3 = 0; // Control for the divide-by-two and x1 functions.//
579	X2sel_32to36_3 = 0; // Control for the x2 function.//
580	X2sel_37to41_3 = 0; // Control for the x2 function.//
581	X4sel_32to36_3 = 0; // Control for the x4 function.//
582	X4sel_37to41_3 = 0; // Control for the x4 function.//
583	X8sel_32to36_3 = 0; // Bit 41 is used for a fine line windowing control bit. If the fine line is needed, this bit needs to be set high if Fout is close to Fref (greater than ~ 950 MHz) or for some testing modes like pass through or thru_rise_en.//
584	X8sel_41_3 = 0; // hiFout - set for passthrough and Fout close to Fref//
585	X8sel_37to40_3 = 0; // //
586	qurx_180Cal_en = 0; // Enables the pad driver that sends the falling edge signal off chip. This falling edge signal is used internally to trigger the 'Reset' pin of the output RS Flip Flop.//
587	qurx_0Cal_en = 0; // Enables the pad driver that sends the rising edge signal off chip. This rising edge signal is used internally to trigger the 'Set' pin of the output RS Flip Flop.//
588	// -------------------------------------------------------------------------------------------------------
589	// PLL
590	// -------------------------------------------------------------------------------------------------------
591	extClkEn = 0; // PLL Reg 0//
592	extClkEnBNOTD7 = 1; // on//
593	div2_rst = 1; // on//
594	TxChClkSel = 0; // //
595	TxChClkEn = 0; // PLL Reg 1//
596	// -------------------------------------------------------------------------------------------------------
597	// TRANSMITTER
598	// -------------------------------------------------------------------------------------------------------
599	tx_bb_en = 0; // BB Fdbk Mux Buffer BW Control. Enables the Forward BB Reference Section of TX//
600	tx_bb_fdbk_bw = 0; // Sets the BW of the BB Correction feedback amp//
601	tx_bb_fdbk_cal_en = 0; // BB Feedback Mux path Routing. Shorts the BB Correction feedback Amp input for self-calibration//
602	tx_bb_fdbk_cart_err_en = 0; // Routes the Cartesian error signal through the BB Correction feedback//
603	tx_bb_fdbk_cart_fb_en = 0; // Routes the Cartesian feedback signal through the BB Correction feedback//
604	tx_bb_fdbk_cart_fwd_en = 0; // Routes the Cartesian reference signal through the BB Correction feedback//
605	tx_bb_fdbk_en = 0; // BB Feedback Mux path Routing. Enables the BB Correction feedback path via the RX pins//
606	tx_bb_fdbk_1q_sel = 0; // Chooses between I or Q channel for the BB Correction feedback path//
607	tx_bb_fdbk_lp = 0; // BB Fdbk Mux Buffer current. Sets the current drive capability for BB Correction feedback Amp//
608	tx_bb_fdbk_statt = 3; // BB Fdbk Mux Buffer Gain Control. BB Feedback Attenuator. Sets the voltage gain for BB Correction feedback Amp//
609	tx_bb_fdbk_swapi = 0; // Baseband Feedback Swap I & Ix. Swaps the I and Ix BB signals through the BB Correction feedback path//
610	tx_bb_fdbk_swapq = 0; // Baseband feedback Swap Q & Qx. Swaps the Q and Qx BB signal through the BB Correction feedback path//
611	tx_bb_gain_cmp = 1; // Baseband Gain 1 dB Compensation. Adds and extra 1.3 dB of Forward Baseband Reference Gain//
612	tx_bb_lp = 0; // BB ref. stage current. BB Amp Stage Current. Sets the current drive capability for Forward BB Reference Amps//
613	tx_bb_swapi = 1; // Baseband Swap I & Ix. Swaps the I and Ix BB signals through the Forward BB Reference Path//
614	tx_bb_swapq = 0; // Baseband Swap Q & Qx. Swaps the Q and Qx BB signals through the Forward BB Reference Path//
615	tx_butt_bw = 0; // BB ref. Butterworth filter BW control. Sets the BW of the Forward BB Reference 4-pole Butterworth Filters//
616	tx_bw_trck = 5; // TX MIM cap tracking filter BW. Bandwidth Tracking. Sets tracking BW of all the MIM cap based TX Filters (16 states)//
617	tx_cart_en = 0; // Cartesian FB path Enable. Enables the Cartesian Baseband Section of Tx//
618	tx_cart_fb_bb_statt = 15; // Cartesian down-mix path BB gain. Cartesian FB path BB gain. Sets the voltage gain for Cartesian BB down converter PMA//
619	tx_cart_fb_dcoc_dac_I1 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC I1//
620	tx_cart_fb_dcoc_dac_I2 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC I2//
621	tx_cart_fb_dcoc_dac_Q1 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC Q1//
622	tx_cart_fb_dcoc_dac_Q2 = 32; // Sets Cartesian BB down converter PMA Dc offset correction DAC Q2//
623	CartesianFeedbackpathDCOCenable = 0; // Cartesian down-mix path BB BW//
624	CartesianFeedbackpathenable = 0; // off//
625	CartesianFBpathHiResolutionDCOCenable = 0; // off//
626	CartesianFBpathBW = 15; // //
627	CartesianFBRFGain = 0; // Cartesian down conv. path RF Gain//
628	CartesianFBpathSwapIandIx = 0; // Swap I & Ix BB in Down Converter//
629	CartesianFBpathSwapQandQx = 0; // off//
630	CartesianFBpathSwitchtoforwardSummer = 0; // off//
631	tx_cart_fb_lo_select = 0; // Cart. down conv LO curr. (tied to Gain)//
632	CartesianFBpathAmp1Gain = 3; // //
633	CartesianFBpathAmp2Gain = 3; // //
634	CartesianFBpathAmp3Gain = 3; // //
635	CartesianFBpathAmp4Gain = 3; // //
636	CartesianFBpathAmpCurrentSelect = 7; // //
637	CartesianFBpathZeroEnable = 0; // off//
638	tx_cart_zero_statt = 1; // Cartesian FB path Zero Gain. Sets the voltage gain for Cartesian Forward BB Zero Amp//
639	tx_inbuf_bw = 0; // Sets the BW of the Forward BB Reference Input Buffers//
640	tx_inbuf_statt = 0; // Sets the attenuation of the Forward BB Ref. Buffers//
641	tx_output_channel_sel = 0; // Selects from the 3 RF Forward TX output paths, 000 is full power down//
642	tx_p1_bw = 0; // Sets the BW of the Cartesian Forward BB Loop Pole 1//
643	tx_pw_bw1 = 0; // Cartesian FB path Pole 2 Bandwidth. Sets the BW of the Cartesian Forward BB Loop Pole 2//
644	tx_p2_bw2 = 0; // Cartesian FB path Pole 2 Bandwidth. Sets the BW of the Cartesian Forward BB Loop Pole 2//
645	PushPullBufferCurrent = 7; // //
646	tx_rf_aoc_bw = 0; // Sets the BW of the AOC control line//
647	RFForwardPathEnable_toMUX = 0; // off//
648	RFForwardPathEnable_ExternalPinenable = 1; // on//
649	tx_rf_fwd_lp = 0; // RF Forward Bias Reference Control. RF Forward Path Current Drain Select. Sets the current drive capability for Forward RF Output Drivers//
650	tx_rf_fwd_statt1 = 0; // RF Passive Step Attenuator control. RF Forward Path Step Attn1. Sets the attenuation level for the RF Step attenuators//
651	tx_rf_fwd_statt2 = 0; // RF Output Driver Step Attn. Control. RF Forward Path Step Attn2. Sets the attenuation level for the RF Output Drivers//
652	BBQDivideby2or4Select = 0; // BBQ Quad Gen Divide by 2 or 4 (High=1/4)//
653	BBQQuadGenEnable = 0; // Bypass Quiet LO with external LO//
654	BBQPolyphaseQuadGenEnable = 0; // off//
655	lofb_tun_s = 8; // //
656	lofb_tun_sx = 8; // //
657	lofw_tun_s2 = 8; // //
658	lofw_tun_sx2 = 8; // //
659	reserve_tx26 = 0; // //
660	reserve_tx27 = 0; // //
661	// -------------------------------------------------------------------------------------------------------
662	// RECEIVER
663	// -------------------------------------------------------------------------------------------------------
664	rx_Idac = 16; // I path DCOC DAC setting. Digital values for the DC offset adjustment. 11111 represents the maximum positive offset adjust and 00000 represents the maximum negative offset adjust. By design, codes 10000 and 01111 cause no change in the offset voltage.//
665	rx_dcs = 0; // DCOC step size select. Selects the proper current reference in the DAC to maintain constant step size at ouptut of baseband filters. This value works in tandem with the BiQuad Gain Select (address 198, bits 4:3) to maintain a constant step size of 24 mV at filter output.//
666	rx_den = 0; // Enables the DC offset correction DACs in the I and Q path.//
667	rx_Qdac = 12; // Q path DCOC DAC setting. Digital values for the DC offset adjustment. 11111 represents the maximum positive offset adjust and 00000 represents the maximum negative offset adjust. By design, codes 10000 and 01111 cause no change in the offset voltage.//
668	rx_cmpen = 0; // Enables the DC offset correction comparator used in the DCOC circuitry.//
669	rx_dcoc = 0; // Enables the DC offset correction circuitry for automatic correction of the DC offset in the baseband filters.//
670	rx_ten = 0; // Enables the RC tuning circuit to tune RX and TX baseband filters.//
671	rx_ren = 0; // Enables the ramp circuit used in the RC tuning circuitry to tune the RX and TX baseband filters.//
672	rx_dven = 0; // //
673	rx_dv = 0; // DCOC/tune clock divider select. Selects the clock rate used for clocking the DCOC and RC tuning circuit. Bits 3 and 2 set the divider setting used for both the DCOC circuitry and RC Tune circuitry. Bits 1 and 0 set the divider setting for the dedicated divider in the DCOC circuitry. Table below shows the mapping of divider settings. The DCOC clock divider setting is the total divide ratio of both dividers. The maximum divide ratio is 8*8 = 64.//
674	rx_extc = 0; // Enables the external capacitor pins to allow for external low-frequency pole to be placed in the signal path between the mixer and baseband filter.//
675	rx_cen = 0; // Chopper enable for filter stages. Settings to enable which amplifier the clock is being applied//
676	rx_chck = 0; // Divider setting for the chopper clock//
677	rx_chcken = 0; // Enables the baseband filter chopper clock.//
678	rx_fen = 0; // Enables baseband filters. 0 puts filter in power save mode.//
679	rx_onchen = 0; // Enables on-channel detector.//
680	rx_offchen = 0; // Enables off-channel detector//
681	rx_foe = 0; // Enables the output of the baseband filters. Otherwise the baseband filter outputs are in a Hi-Z state to allow transmitter to use filter output pins. When Filter Enable is set LOW, outputs are disabled (Hi-Z)//
682	rx_offch = 1; // Sets the Clip Threshold for the Off-channel Detector//
683	rx_onchf = 0; // Sets the Fade Threshold for the On-channel Detector relative to the On-channel clip point.//
684	rx_onchc = 2 ;// Sets the Clip Threshold for the On-channel Detector//
685	rx_qs = 0; // Sets the BiQuad filter Q//
686	rx_bqg = 0; // Set BiQuad filter gain//
687	// FIXME Maybe set rx_rq to 0
688	rx_rq = 1; // Sets the BiQuad filter resistor value. The natural frequency of the BiQuad (wo) is this resistor value multiplied by the BiQuad Capacitor value.//
689	rx_rv = 1; // Sets the VGA filter (passive filter) resistor value. The pole frequency of the passive filter is this resistor value multiplied by the VGA capacitor value.//
690	rx_rip = 0; // Sets the MPA input resistor value that sets the gain of the PMA. Gain of the PMA is Rf/Rin where Rf is the PMA feedback resistor and Rin is the input resistor. Note that the input resistance remains at 2 kohm differential for all settings. An R2R ladder is used to accomplish this while changing the Rin value.//
691	rx_rfp = 2; // Sets the PMA feedback resistor value that sets the gain of the PMA as well as the pole frequency (along with PMA capacitor value). Gain of the PMA is Rf/Rin where Rf is the PMA feedback resistor and Rin is the input resistor.//
692	rx_cp_12to8 = 0; // Sets the PMA filter capacitor value. The pole frequency of the PMA filter is the PMA feedback resistor value multiplied by this Capacitor value. PMA Capacitor (in pF) = (PMAC) * 0.0625 + 1//
693	rx_gs = 0; // Sets the gain of the VGA in the baseband filter//
694	rx_cp_7to0 = 0; // PMA cap select LSBs. Sets the PMA filter capacitor value. The pole frequency of the PMA filter is the PMA feedback resistor value multiplied by this Capacitor value. PMA Capacitor (in pF) = (PMAC) * 0.0625 + 1//
695	rx_cv_10to3 = 0; // VGA cap select MSBs. Sets the VGA (passive) filter capacitor value. This pole frequency of the passive filter is the VGA resistor value multiplied by this Capacitor value. VGA Capacitor (in pF) = (VGAC) * 0.0625 + 1//
696	rx_cv_2to0 = 0; // VGA cap select LSBs. Sets the VGA (passive) filter capacitor value. This pole frequency of the passive filter is the VGA resistor value multiplied by this Capacitor value. VGA Capacitor (in pF) = (VGAC) * 0.0625 + 1//
697	rx_cc_2to0 = 0; // Compensation control. Disables additional compensation capacitance in the VGA and BiQuad op-amps to allow for higher bandwidths. Also increases the op-ampdominate pole-frequency which improves filter response. Bit 4 controls the VGA amplifier, Bit 3 controls the feedback amplifier in the BiQuad, and Bit 2 controls the output buffer in the BiQuad.//
698	rx_cq_9to8 = 0; // BiQuad cap select MSBs. Sets the BiQuad filter capacitor value. The natural frequency of the BiQuad (wo) is the BiQuad resistor value multiplied by this Capacitor value. BiQuad Capacitor (in pF) = (BiQuadC) * 0.125 + 2//
699	rx_cq_7to0 = 0; // BiQuad cap select LSBs. Sets the BiQuad filter capacitor value. The natural frequency of the BiQuad (wo) is the BiQuad resistor value multiplied by this Capacitor value. BiQuad Capacitor (in pF) = (BiQuadC) * 0.125 + 2//
700	rx_lna = 1; // LNA select//
701	rx_lnab = 0; // LNA bias select//
702	rx_rxchen = 0; // RX mixer enable. Must be set to 1 to enable Mixer operation//
703	rx_bbq_div2or4 = 0; // Selects divide ratio of RX Quad Gen when using external LO. 0->DIV2, 1 ->DIV1//
704	rx_Loselect = 0; // RX external LO select. Enables external LO clock source//
705	poly_en = 0; // off//
706	lorx_tun_s = 8; // //
707	lorx_tun_sx = 8; // //
708
709	shft_cml_in = 0; //Enable - 150mV level shift of Ref. BB VAG//
710	vagenable1 = 1; //Enable VAG Gen into Sleep Mode (slow ramp up)//
711	vagenable2 = 1; //Enable VAG Gen in Full On Mode (Fast ramp from sleep)//
712	//-------------------------------------------------------------------------------------------------------
713	// TEST MULTIPLEXER
714	//-------------------------------------------------------------------------------------------------------
715	TestMuxBufferEnable = 0; //Enable Test Mux Buffer//
716	TestMuxEnable = 0; //Enable Test Mux//
717	TestMuxSetting = 0; //Four Output Description (Test1, Test2, Test3, Test4)//
718	txgain = 0; //Set Transmit Gain//
719	Fclk = 1000e6; //Default clock frequency, in Hz//
720
721	Fouttx = 0; // Default tx frequency is zero//
722	Foutrx = 0; // Default rx frequency is zero//
723	Foutfb = 0; // Default feedback frequency is zero//
724
725	// Initialize GPIO and ATR
726	// GPIO are the general-purpose IO pins on the daughterboard
727	// IO_RX_06 must be used for ATR (1 = TX, 0 = RX)
728	// ATR is the automatic transmit/receive switching, done in the FPGA
729	// FIXME
730
731
732	rx_write_io(0, TX_EN);
733	rx_write_oe(TX_EN, TX_EN);
734	rx_set_atr_rxval(0);
735	rx_set_atr_txval(TX_EN);
736	rx_set_atr_mask(TX_EN);
737
738	d_spi_format = SPI_FMT_MSB \| SPI_FMT_HDR_2;
739	d_spi_format_no_header = SPI_FMT_MSB \| SPI_FMT_HDR_0;
740
741	if (int(which) == 0)
742	d_spi_enable = SPI_ENABLE_RX_A;
743	else
744	d_spi_enable = SPI_ENABLE_RX_B;
745
746	}
747
748	rfic::~rfic()
749	{
750	//printf("rfic::destructor\n");
751	shutdown();
752	}
753
754	void
755	rfic::shutdown()
756	{
757	Rst_n_async = 0;
758	set_reg_24();
759	Rst_n_async2 = 0;
760	set_reg_72();
761	Rst_n_async3 = 0;
762	set_reg_128();
763
764	X1sel_32to39_3 = 0;
765	X1sel_40to47_3 = 0;
766	X2sel_32to36_3 = 0;
767	X2sel_37to41_3 = 0;
768	X4sel_32to36_3 = 0;
769	X4sel_37to41_3 = 0;
770
771	set_reg_139();
772	set_reg_140();
773	set_reg_141();
774	set_reg_142();
775	set_reg_143();
776	set_reg_144();
777
778	X1sel_32to39 = 0;
779	X1sel_40to47 = 0;
780	X2sel_32to36 = 0;
781	X2sel_37to41 = 0;
782	X4sel_32to36 = 0;
783	X4sel_37to41 = 0;
784
785	set_reg_35();
786	set_reg_36();
787	set_reg_37();
788	set_reg_38();
789	set_reg_39();
790	set_reg_40();
791
792	X1sel_32to39_2 = 0;
793	X1sel_40to47_2 = 0;
794	X2sel_32to36_2 = 0;
795	X2sel_37to41_2 = 0;
796	X4sel_32to36_2 = 0;
797	X4sel_37to41_2 = 0;
798
799	set_reg_83();
800	set_reg_84();
801	set_reg_85();
802	set_reg_86();
803	set_reg_87();
804	set_reg_88();
805
806	// --------------------------------------------------------------------
807	// These methods set the RFIC onboard registers over the SPI bus.
808	// Thus, the shift values here are the 0-7 values from the data sheet
809
810	// For more information about setting each variable and SPI register, see RFIC4 SPI Default Variables.xls
811
812
813	///////////////////////////////////have to do this after i finish all the set reg functions///////////////////////////////////
814	}
815
816	bool
817	rfic::rx_write_oe(int value,int mask){
818
819	if (int(d_which) == 0)
820	return usrp()->_write_fpga_reg(FR_OE_1, (mask << 16) \| value);
821	else
822	return usrp()->_write_fpga_reg(FR_OE_3, (mask << 16) \| value);
823	}
824
825	bool
826	rfic::rx_write_io(int value,int mask){
827
828	if (int(d_which) == 0)
829	return usrp()->_write_fpga_reg(FR_IO_1, (mask << 16) \| value);
830	else
831	return usrp()->_write_fpga_reg(FR_IO_3, (mask << 16) \| value);
832
833	}
834
835	bool
836	rfic::rx_set_atr_mask(int value){
837
838	if (int(d_which) == 0)
839	return usrp()->_write_fpga_reg(FR_ATR_MASK_1, value);
840	else
841	return usrp()->_write_fpga_reg(FR_ATR_MASK_3, value);
842
843	}
844
845	bool
846	rfic::rx_set_atr_txval(int value){
847
848	if (int(d_which) == 0)
849	return usrp()->_write_fpga_reg(FR_ATR_TXVAL_1, value);
850	else
851	return usrp()->_write_fpga_reg(FR_ATR_TXVAL_3, value);
852	}
853
854	bool
855	rfic::rx_set_atr_rxval(int value){
856
857	if (int(d_which) == 0)
858	return usrp()->_write_fpga_reg(FR_ATR_RXVAL_1, value);
859	else
860	return usrp()->_write_fpga_reg(FR_ATR_RXVAL_3, value);
861
862	}
863
864
865
866
867
868
869	void
870	rfic::send_reg(int reg_no,int dat )
871	{
872	std::cout<<"value to be written on reg no "<<reg_no<<"is "<<dat<<std::endl;
873	// dat is the data to write to register 0
874	//spi_enable is the spi enables
875	//spi_format is the spi format with a two-byte header
876	//spi_format_no_header is the spi format, with no header
877	//Send 16 bit header over SPI to send register number
878	//Write 8 bit register
879	//Set header
880	int hdr = int( (reg_no << 1) & 0x7fff);
881	//Set byte of write data
882	char c = (char)((dat & 0xff));
883	char * d = &c;
884	bool check;
885	std::cout<<"\nValue on the register before writing\n"<<get_reg(reg_no)<<std::endl;
886	check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, d);
887	std::cout<<"\nValue on the register after ******** writing\n"<<get_reg(reg_no)<<std::endl;
888
889	}
890
891	char
892	rfic::get_reg(int reg_num)
893	{
894
895	std::cout<<"inside get reg and register to be read is "<<reg_num<<std::endl;
896	//Returns a vector containing the information in the first 320 registers in integer form
897	//dat is the data to write to register 0
898	//spi_enable is the spi enables
899	//spi_format is the spi format with a two-byte header
900	//spi_format_no_header is the spi format, with no header
901	//u is the instance of the USRP
902	int hdr = 0;
903	int dat = 0;
904	//Set byte of write data
905	char c = (char)((dat & 0xff));
906	char * d = &c;
907	bool check;
908	check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, d);
909
910	std::string r; //string to be read from the register
911	r = usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
912	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
913	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
914	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
915	r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64);
916	std::cout<<"the contents of all registers are\n"<<r<<std::endl;
917	char read_val = (char)r[reg_num];
918	return read_val;
919	}
920
921	void rfic :: set_reg_205(){
922	int reg_205 = (
923	rx_lna << 5 \|
924	rx_lnab << 3 \|
925	rx_rxchen << 2 \|
926	rx_bbq_div2or4 << 1 \|
927	rx_Loselect << 0 );
928	send_reg(205, reg_205);
929	}
930
931	void rfic :: set_reg_0(){
932	int reg_0 = (
933	Ngt3 << 7 \|
934	NorNdiv4 << 0 );
935	send_reg(0, reg_0);
936	}
937
938	void rfic :: set_reg_1(){
939	int reg_1 = (
940	RorFrNpRdiv4_25to18 << 0 );
941	send_reg(1, reg_1);
942	}
943
944
945	void rfic :: set_reg_2(){
946	int reg_2 = (
947	RorFrNpRdiv4_17to10 << 0 );
948	send_reg(2, reg_2);
949	}
950
951	void rfic :: set_reg_3(){
952	int reg_3 = (
953	RorFrNpRdiv4_9to2 << 0 );
954	send_reg(3, reg_3);
955	}
956
957
958	void rfic :: set_reg_4(){
959	int reg_4 = (
960	RorFrNpRdiv4_1to0 << 6 );
961	send_reg(4, reg_4);
962	}
963	void rfic :: set_reg_5(){
964	int reg_5 = (
965	Qu_tx_Ngt3 << 7 \|
966	NorNdiv4_phsh << 0 );
967	send_reg(5, reg_5);
968	}
969
970	void rfic :: set_reg_6(){
971	int reg_6 = (
972	RorFrNpRdiv4_phsh_25to18 << 0 );
973	send_reg(6, reg_6);
974	}
975
976	void rfic :: set_reg_7(){
977	int reg_7 = (
978	RorFrNpRdiv4_phsh_17to10 << 0 );
979	send_reg(7, reg_7);
980	}
981
982	void rfic :: set_reg_8(){
983	int reg_8 = (
984	RorFrNpRdiv4_phsh_9to2 << 0 );
985	send_reg(8, reg_8);
986	}
987
988	void rfic :: set_reg_9(){
989	int reg_9 = (
990	RorFrNpRdiv4_phsh_1to0 << 6 );
991	send_reg(9, reg_9);
992	}
993
994	void rfic :: set_reg_10(){
995	int reg_10 = (
996	Passthru_ref_clk << 7 \|
997	Byp_ram << 6 \|
998	Dis_adr_dith << 5 \|
999	Dis_p5G_dith << 4 \|
1000	Byp_fine << 3 \|
1001	Exclude32 << 2 \|
1002	Dis_risedge << 1 \|
1003	Dis_faledge << 0 );
1004	send_reg(10, reg_10);
1005	}
1006
1007
1008	void rfic :: set_reg_12(){
1009	int reg_12 = (
1010	Spr_puls_en << 7 \|
1011	Spr_puls_val_a_9to3 << 0 );
1012	send_reg(12, reg_12);
1013	}
1014
1015	void rfic :: set_reg_13(){
1016	int reg_13 = (
1017	Spr_pulse_val_2to0 << 5 );
1018	send_reg(13, reg_13);
1019	}
1020
1021	void rfic :: set_reg_14(){
1022	int reg_14 = (
1023	Spr_puls_val_b_9to2 << 0 );
1024	send_reg(14, reg_14);
1025	}
1026
1027	void rfic :: set_reg_15(){
1028	int reg_15 = (
1029	Spr_puls_val_b_1to0 << 6 );
1030	send_reg(15, reg_15);
1031	}
1032
1033
1034	void rfic :: set_reg_16(){
1035	int reg_16 = (
1036	Thru_ris_en << 7 \|
1037	Thru_ris_tap_11to6 << 1 );
1038	send_reg(16, reg_16);
1039	}
1040
1041	void rfic :: set_reg_17(){
1042	int reg_17 = (
1043	Thru_ris_tap_5to0 << 2 );
1044	send_reg(17, reg_17);
1045	}
1046
1047	void rfic :: set_reg_18(){
1048	int reg_18 = (
1049	Thru_fal_en << 7 \|
1050	Thru_fal_tap_11to6 << 1 );
1051	send_reg(18, reg_18);
1052	}
1053	void rfic :: set_reg_19(){
1054	int reg_19 = (
1055	Thru_fal_tap_5to0 << 2 );
1056	send_reg(19, reg_19);
1057	}
1058	void rfic :: set_reg_20(){
1059	int reg_20 = (
1060	Dig_delay << 7 \|
1061	Clk_driver_en << 6 \|
1062	qu_reg_en << 5 \|
1063	qq_reg_en << 4 \|
1064	win_rst << 3 \|
1065	fineEn << 2 \|
1066	fineEnb << 1 \|
1067	rsffEn << 0 );
1068	send_reg(20, reg_20);
1069	}
1070
1071	void rfic :: set_reg_21(){
1072	int reg_21 = (
1073	dl_en << 7 \|
1074	cp_en << 6 \|
1075	forceCpUpb << 5 \|
1076	forceCpDn << 4 \|
1077	pdUpTune_1to0 << 2 \|
1078	pdDnTune_1to0 << 0 );
1079	send_reg(21, reg_21);
1080	}
1081
1082	void rfic :: set_reg_22(){
1083	int reg_22 = (
1084	cpUpTune_2to0 << 5 \|
1085	cpDnTune_2to0 << 2 \|
1086	pdEn << 1 );
1087	send_reg(22, reg_22);
1088	}
1089
1090	void rfic :: set_reg_23(){
1091	int reg_23 = (
1092	digClkPhase_7to0 << 0 );
1093	send_reg(23, reg_23);
1094	}
1095	void rfic :: set_reg_24(){
1096	int reg_24 = (
1097	Rst_n_async << 7 );
1098	send_reg(24, reg_24);
1099	}
1100	void rfic :: read_reg_25(){
1101	int reg_25 = get_reg(25);
1102	L1_lup00_15to8 = reg_25;
1103	}
1104	void rfic :: read_reg_26(){
1105	int reg_26 = get_reg(26);
1106	L1_lup90_15to8 = reg_26;
1107	}
1108	void rfic :: read_reg_27(){
1109	int reg_27 = get_reg(27);
1110	Merg_ris_fin = reg_27 >> 2;
1111	}
1112	void rfic :: read_reg_28(){
1113	int reg_28 = get_reg(28);
1114	Merg_fal_fin = reg_28 >> 2;
1115	}
1116	void rfic :: set_reg_29(){
1117	int reg_29 = (
1118	Qg00degDelay_0to4 << 3 );
1119	send_reg(29, reg_29);
1120	}
1121	void rfic :: set_reg_30(){
1122	int reg_30 = (
1123	Qg90degDelay_0to4 << 3 );
1124	send_reg(30, reg_30);
1125	}
1126	void rfic :: set_reg_31(){
1127	int reg_31 = (
1128	Qg180degDelay_0to4 << 3 );
1129	send_reg(31, reg_31);
1130	}
1131	void rfic :: set_reg_32(){
1132	int reg_32 = (
1133	Qg270degDelay_0to4 << 3 );
1134	send_reg(32, reg_32);
1135	}
1136	void rfic :: set_reg_33(){
1137	int reg_33 = (
1138	DischargeTap16_0to3 << 4 \|
1139	ChargeTap16_0to3 << 0 );
1140	send_reg(33, reg_33);
1141	}
1142	void rfic :: set_reg_34(){
1143	int reg_34 = (
1144	DischargeTapn_0to3 << 4 \|
1145	ChargeTapn16_0to3 << 0 );
1146	send_reg(34, reg_34);
1147	}
1148	void rfic :: set_reg_35(){
1149	int reg_35 = (
1150	X1sel_32to39 << 0 );
1151	send_reg(35, reg_35);
1152	}
1153	void rfic :: set_reg_36(){
1154	int reg_36 = (
1155	X1sel_40to47 << 0 );
1156	send_reg(36, reg_36);
1157	}
1158	void rfic :: set_reg_37(){
1159	int reg_37 = (
1160	X2sel_32to36 << 3 );
1161	send_reg(37, reg_37);
1162	}
1163	void rfic :: set_reg_38(){
1164	int reg_38 = (
1165	X2sel_37to41 << 3 );
1166	send_reg(38, reg_38);
1167	}
1168	void rfic :: set_reg_39(){
1169	int reg_39 = (
1170	X4sel_32to36 << 3 );
1171	send_reg(39, reg_39);
1172	}
1173	void rfic :: set_reg_40(){
1174	int reg_40 = (
1175	X4sel_37to41 << 3 );
1176	send_reg(40, reg_40);
1177	}
1178	void rfic :: set_reg_41(){
1179	int reg_41 = (
1180	X8sel_32to36 << 3 );
1181	send_reg(41, reg_41);
1182	}
1183	void rfic :: set_reg_42(){
1184	int reg_42 = (
1185	X8sel_41 << 7 \|
1186	X8sel_37to40 << 3 );
1187	send_reg(42, reg_42);
1188	}
1189	void rfic :: set_reg_43(){
1190	int reg_43 = (
1191	qutx_fwd_180Cal_en << 7 \|
1192	qutx_fwd_0Cal_en << 6 );
1193	send_reg(43, reg_43);
1194	}
1195	void rfic :: set_reg_48(){
1196	int reg_48 = (
1197	Ngt3_2 << 7 \|
1198	NorNdiv4_2 << 0 );
1199	send_reg(48, reg_48);
1200	}
1201	void rfic :: set_reg_49(){
1202	int reg_49 = (
1203	RorFrNpRdiv4_25to18_2 << 0 );
1204	send_reg(49, reg_49);
1205	}
1206	void rfic :: set_reg_50(){
1207	int reg_50 = (
1208	RorFrNpRdiv4_17to10_2 << 0 );
1209	send_reg(50, reg_50);
1210	}
1211	void rfic :: set_reg_51(){
1212	int reg_51 = (
1213	RorFrNpRdiv4_9to2_2 << 0 );
1214	send_reg(51, reg_51);
1215	}
1216	void rfic :: set_reg_52(){
1217	int reg_52 = (
1218	RorFrNpRdiv4_1to0_2 << 6 );
1219	send_reg(52, reg_52);
1220	}
1221	void rfic :: set_reg_53(){
1222	int reg_53 = (
1223	Qu_tx_Ngt3_2 << 7 \|
1224	NorNdiv4_phsh_2 << 0 );
1225	send_reg(52, reg_53);
1226	}
1227	void rfic :: set_reg_54(){
1228	int reg_54 = (
1229	RorFrNpRdiv4_phsh_25to18_2 << 0 );
1230	send_reg(54, reg_54);
1231	}
1232	void rfic :: set_reg_55(){
1233	int reg_55 = (
1234	RorFrNpRdiv4_phsh_17to10_2 << 0 );
1235	send_reg(55, reg_55);
1236	}
1237	void rfic :: set_reg_56(){
1238	int reg_56 = (
1239	RorFrNpRdiv4_phsh_9to2_2 << 0 );
1240	send_reg(56, reg_56);
1241	}
1242	void rfic :: set_reg_57(){
1243	int reg_57 = (
1244	RorFrNpRdiv4_phsh_1to0_2 << 6 );
1245	send_reg(57, reg_57);
1246	}
1247	void rfic :: set_reg_58(){
1248	int reg_58 = (
1249	Passthru_ref_clk_2 << 7 \|
1250	Byp_ram_2 << 6 \|
1251	Dis_adr_dith_2 << 5 \|
1252	Dis_p5G_dith_2 << 4 \|
1253	Byp_fine_2 << 3 \|
1254	Exclude32_2 << 2 \|
1255	Dis_risedge_2 << 1 \|
1256	Dis_faledge_2 << 0 );
1257	send_reg(58, reg_58);
1258	}
1259	void rfic :: set_reg_60(){
1260	int reg_60 = (
1261	Spr_puls_en_2 << 7 \|
1262	Spr_puls_val_a_9to3_2 << 0 );
1263	send_reg(60, reg_60);
1264	}
1265	void rfic :: set_reg_61(){
1266	int reg_61 = (
1267	Spr_pulse_val_2to0_2 << 5 );
1268	send_reg(61, reg_61);
1269	}
1270	void rfic :: set_reg_62(){
1271	int reg_62 = (
1272	Spr_puls_val_b_9to2_2 << 0 );
1273	send_reg(62, reg_62);
1274	}
1275	void rfic :: set_reg_63(){
1276	int reg_63 = (
1277	Spr_puls_val_b_1to0_2 << 6 );
1278	send_reg(63, reg_63);
1279	}
1280	void rfic :: set_reg_64(){
1281	int reg_64 = (
1282	Thru_ris_en_2 << 7 \|
1283	Thru_ris_tap_11to6_2 << 1 );
1284	send_reg(64, reg_64);
1285	}
1286	void rfic :: set_reg_65(){
1287	int reg_65 = (
1288	Thru_ris_tap_5to0_2 << 2 );
1289	send_reg(65, reg_65);
1290	}
1291	void rfic :: set_reg_66(){
1292	int reg_66 = (
1293	Thru_fal_en_2 << 7 \|
1294	Thru_fal_tap_11to6_2 << 1 );
1295	send_reg(66, reg_66);
1296	}
1297	void rfic :: set_reg_67(){
1298	int reg_67 = (
1299	Thru_fal_tap_5to0_2 << 2 );
1300	send_reg(67, reg_67);
1301	}
1302	void rfic :: set_reg_68(){
1303	int reg_68 = (
1304	Dig_delay_2 << 7 \|
1305	Clk_driver_en_2 << 6 \|
1306	qu_reg_en_2 << 5 \|
1307	qq_reg_en_2 << 4 \|
1308	win_rst_2 << 3 \|
1309	fineEn_2 << 2 \|
1310	fineEnb_2 << 1 \|
1311	rsffEn_2 << 0 );
1312	send_reg(68, reg_68);
1313	}
1314	void rfic :: set_reg_69(){
1315	int reg_69 = (
1316	dl_en_2 << 7 \|
1317	cp_en_2 << 6 \|
1318	forceCpUpb_2 << 5 \|
1319	forceCpDn_2 << 4 \|
1320	pdUpTune_1to0_2 << 2 \|
1321	pdDnTune_1to0_2 << 0 );
1322	send_reg(69, reg_69);
1323	}
1324	void rfic :: set_reg_70(){
1325	int reg_70 = (
1326	cpUpTune_2to0_2 << 5 \|
1327	cpDnTune_2to0_2 << 2 \|
1328	pdEn_2 << 1 );
1329	send_reg(70, reg_70);
1330	}
1331	void rfic :: set_reg_71(){
1332	int reg_71 = (
1333	digClkPhase_7to0_2 << 0 );
1334	send_reg(71, reg_71);
1335	}
1336	void rfic :: set_reg_72(){
1337	int reg_72 = (
1338	Rst_n_async_2 << 7 );
1339	send_reg(72, reg_72);
1340	}
1341	void rfic :: read_reg_73(){
1342	int reg_73 = get_reg(73);
1343	L1_lup00_15to8_2 = reg_73;
1344	}
1345	void rfic :: read_reg_74(){
1346	int reg_74 = get_reg(74);
1347	L1_lup90_15to8_2 = reg_74;
1348	}
1349	void rfic :: read_reg_75(){
1350	int reg_75 = get_reg(75);
1351	Merg_ris_fin_2 = reg_75 >> 2;
1352	}
1353	void rfic :: read_reg_76(){
1354	int reg_76 = get_reg(76);
1355	Merg_fal_fin_2 = reg_76 >> 2;
1356	}
1357	void rfic :: set_reg_77(){
1358	int reg_77 = (
1359	Qg00degDelay_0to4_2 << 3 );
1360	send_reg(77, reg_77);
1361	}
1362	void rfic :: set_reg_78(){
1363	int reg_78 = (
1364	Qg90degDelay_0to4_2 << 3 );
1365	send_reg(78, reg_78);
1366	}
1367	void rfic :: set_reg_79(){
1368	int reg_79 = (
1369	Qg180degDelay_0to4_2 << 3 );
1370	send_reg(79, reg_79);
1371	}
1372	void rfic :: set_reg_80(){
1373	int reg_80 = (
1374	Qg270degDelay_0to4_2 << 3 );
1375	send_reg(80, reg_80);
1376	}
1377	void rfic :: set_reg_81(){
1378	int reg_81 = (
1379	DischargeTap16_3to0 << 4 \|
1380	ChargeTap16_3to0 << 0 );
1381	send_reg(81, reg_81);
1382	}
1383	void rfic :: set_reg_82(){
1384	int reg_82 = (
1385	DischargeTapn_3to0 << 4 \|
1386	ChargeTapn16_3to0 << 0 );
1387	send_reg(82, reg_82);
1388	}
1389	void rfic :: set_reg_83(){
1390	int reg_83 = (
1391	X1sel_32to39_2 << 0 );
1392	send_reg(83, reg_83);
1393	}
1394	void rfic :: set_reg_84(){
1395	int reg_84 = (
1396	X1sel_40to47_2 << 0 );
1397	send_reg(84, reg_84);
1398	}
1399	void rfic :: set_reg_85(){
1400	int reg_85 = (
1401	X2sel_32to36_2 << 3 );
1402	send_reg(85, reg_85);
1403	}
1404	void rfic :: set_reg_86(){
1405	int reg_86 = (
1406	X2sel_37to41_2 << 3 );
1407	send_reg(86, reg_86);
1408	}
1409	void rfic :: set_reg_87(){
1410	int reg_87 = (
1411	X4sel_32to36_2 << 3 );
1412	send_reg(87, reg_87);
1413	}
1414	void rfic :: set_reg_88(){
1415	int reg_88 = (
1416	X4sel_37to41_2 << 3 );
1417	send_reg(88, reg_88);
1418	}
1419	void rfic :: set_reg_89(){
1420	int reg_89 = (
1421	X8sel_32to36_2 << 3 );
1422	send_reg(89, reg_89);
1423	}
1424	void rfic :: set_reg_90(){
1425	int reg_90 = (
1426	X8sel_41_2 << 7 \|
1427	X8sel_37to40_2 << 3 );
1428	send_reg(90, reg_90);
1429	}
1430	void rfic :: set_reg_91(){
1431	int reg_91 = (
1432	qutx_fb_180Cal_en << 7 \|
1433	qutx_fb_0Cal_en << 6 \|
1434	qutx_fb_180Rsff_en << 5 \|
1435	qutx_fb_0Rsff_en << 4 );
1436	send_reg(91, reg_91);
1437	}
1438	void rfic :: set_reg_96(){
1439	int reg_96 = (
1440	N << 4 \|
1441	R_11to8 << 0 );
1442	send_reg(96, reg_96);
1443	}
1444	void rfic :: set_reg_97(){
1445	int reg_97 = (
1446	R_7to0 << 0 );
1447	send_reg(97, reg_97);
1448	}
1449	void rfic :: set_reg_98(){
1450	int reg_98 = (
1451	Asyncrst_n << 7 \|
1452	Cp_sel_6to0 << 0 );
1453	send_reg(98, reg_98);
1454	}
1455	void rfic :: set_reg_99(){
1456	int reg_99 = (
1457	Cp_sel_8to7 << 6 \|
1458	ForceFout << 5 \|
1459	ForceFoutb << 4 \|
1460	Out_en << 3 \|
1461	Dll_en << 2 \|
1462	Ana_en << 1 );
1463	send_reg(99, reg_99);
1464	}
1465	void rfic :: read_reg_100(){
1466	int reg_100 = get_reg(100);
1467	Decod_in_0deg = reg_100 >> 3;
1468	}
1469	void rfic :: set_reg_104(){
1470	int reg_104 = (
1471	Ngt3_3 << 7 \|
1472	NorNdiv4_3 << 0 );
1473	send_reg(104, reg_104);
1474	}
1475	void rfic :: set_reg_105(){
1476	int reg_105 = (
1477	RorFrNpRdiv4_25to18_3 << 0 );
1478	send_reg(105, reg_105);
1479	}
1480	void rfic :: set_reg_106(){
1481	int reg_106 = (
1482	RorFrNpRdiv4_17to10_3 << 0 );
1483	send_reg(106, reg_106);
1484	}
1485	void rfic :: set_reg_107(){
1486	int reg_107 = (
1487	RorFrNpRdiv4_9to2_3 << 0 );
1488	send_reg(107, reg_107);
1489	}
1490	void rfic :: set_reg_108(){
1491	int reg_108 = (
1492	RorFrNpRdiv4_1to0_3 << 6 );
1493	send_reg(108, reg_108);
1494	}
1495	void rfic :: set_reg_109(){
1496	int reg_109 = (
1497	Qu_tx_Ngt3_3 << 7 \|
1498	NorNdiv4_phsh_3 << 0 );
1499	send_reg(109, reg_109);
1500	}
1501	void rfic :: set_reg_110(){
1502	int reg_110 = (
1503	RorFrNpRdiv4_phsh_25to18_3 << 0 );
1504	send_reg(110, reg_110);
1505	}
1506	void rfic :: set_reg_111(){
1507	int reg_111 = (
1508	RorFrNpRdiv4_phsh_17to10_3 << 0 );
1509	send_reg(111, reg_111);
1510	}
1511	void rfic :: set_reg_112(){
1512	int reg_112 = (
1513	RorFrNpRdiv4_phsh_9to2_3 << 0 );
1514	send_reg(112, reg_112);
1515	}
1516	void rfic :: set_reg_113(){
1517	int reg_113 = (
1518	RorFrNpRdiv4_phsh_1to0_3 << 6 );
1519	send_reg(113, reg_113);
1520	}
1521	void rfic :: set_reg_114(){
1522	int reg_114 = (
1523	Passthru_ref_clk_3 << 7 \|
1524	Byp_ram_3 << 6 \|
1525	Dis_adr_dith_3 << 5 \|
1526	Dis_p5G_dith_3 << 4 \|
1527	Byp_fine_3 << 3 \|
1528	Exclude32_3 << 2 \|
1529	Dis_risedge_3 << 1 \|
1530	Dis_faledge_3 << 0 );
1531	send_reg(114, reg_114);
1532	}
1533	void rfic :: set_reg_116(){
1534	int reg_116 = (
1535	Spr_puls_en_3 << 7 \|
1536	Spr_puls_val_a_9to3_3 << 0 );
1537	send_reg(116, reg_116);
1538	}
1539	void rfic :: set_reg_117(){
1540	int reg_117 = (
1541	Spr_pulse_val_2to0_3 << 5 );
1542	send_reg(117, reg_117);
1543	}
1544	void rfic :: set_reg_118(){
1545	int reg_118 = (
1546	Spr_puls_val_b_9to2_3 << 0 );
1547	send_reg(118, reg_118);
1548	}
1549	void rfic :: set_reg_119(){
1550	int reg_119 = (
1551	Spr_puls_val_b_1to0_3 << 6 );
1552	send_reg(119, reg_119);
1553	}
1554	void rfic :: set_reg_120(){
1555	int reg_120 = (
1556	Thru_ris_en_3 << 7 \|
1557	Thru_ris_tap_11to6_3 << 1 );
1558	send_reg(120, reg_120);
1559	}
1560	void rfic :: set_reg_121(){
1561	int reg_121 = (
1562	Thru_ris_tap_5to0_3 << 2 );
1563	send_reg(121, reg_121);
1564	}
1565	void rfic :: set_reg_122(){
1566	int reg_122 = (
1567	Thru_fal_en_3 << 7 \|
1568	Thru_fal_tap_11to6_3 << 1 );
1569	send_reg(122, reg_122);
1570	}
1571	void rfic :: set_reg_123(){
1572	int reg_123 = (
1573	Thru_fal_tap_5to0_3 << 2 );
1574	send_reg(123, reg_123);
1575	}
1576	void rfic :: set_reg_124(){
1577	int reg_124 = (
1578	Dig_delay_3 << 7 \|
1579	Clk_driver_en_3 << 6 \|
1580	qu_reg_en_3 << 5 \|
1581	qq_reg_en_3 << 4 \|
1582	win_rst_3 << 3 \|
1583	fineEn_3 << 2 \|
1584	fineEnb_3 << 1 \|
1585	rsffEn_3 << 0 );
1586	send_reg(124, reg_124);
1587	}
1588	void rfic :: set_reg_125(){
1589	int reg_125 = (
1590	dl_en_3 << 7 \|
1591	cp_en_3 << 6 \|
1592	forceCpUpb_3 << 5 \|
1593	forceCpDn_3 << 4 \|
1594	pdUpTune_1to0_3 << 2 \|
1595	pdDnTune_1to0_3 << 0 );
1596	send_reg(125, reg_125);
1597	}
1598	void rfic :: set_reg_126(){
1599	int reg_126 = (
1600	cpUpTune_2to0_3 << 5 \|
1601	cpDnTune_2to0_3 << 2 \|
1602	pdEn_3 << 1 );
1603	send_reg(126, reg_126);
1604	}
1605	void rfic :: set_reg_127(){
1606	int reg_127 = (
1607	digClkPhase_7to0_3 << 0 );
1608	send_reg(127, reg_127);
1609	}
1610	void rfic :: set_reg_128(){
1611	int reg_128 = (
1612	Rst_n_async_3 << 7 );
1613	send_reg(128, reg_128);
1614	}
1615	void rfic :: read_reg_129(){
1616	int reg_129 = get_reg(129);
1617	L1_lup00_15to8_3 = reg_129;
1618	}
1619	void rfic :: read_reg_130(){
1620	int reg_130 = get_reg(130);
1621	L1_lup90_15to8_3 = reg_130;
1622	}
1623	void rfic :: read_reg_131(){
1624	int reg_131 = get_reg(131);
1625	Merg_ris_fin_3 = reg_131 >> 2;
1626	}
1627	void rfic :: read_reg_132(){
1628	int reg_132 = get_reg(132);
1629	Merg_fal_fin_3 = reg_132 >> 2;
1630	}
1631	void rfic :: set_reg_133(){
1632	int reg_133 = (
1633	Qg00degDelay_0to4_3 << 3 );
1634	send_reg(133, reg_133);
1635	}
1636	void rfic :: set_reg_134(){
1637	int reg_134 = (
1638	Qg90degDelay_0to4_3 << 3 );
1639	send_reg(134, reg_134);
1640	}
1641	void rfic :: set_reg_135(){
1642	int reg_135 = (
1643	Qg180degDelay_0to4_3 << 3 );
1644	send_reg(135, reg_135);
1645	}
1646	void rfic :: set_reg_136(){
1647	int reg_136 = (
1648	Qg270degDelay_0to4_3 << 3 );
1649	send_reg(136, reg_136);
1650	}
1651	void rfic :: set_reg_137(){
1652	int reg_137 = (
1653	DischargeTap16_0to3_3 << 4 \|
1654	ChargeTap16_0to3_3 << 0 );
1655	send_reg(137, reg_137);
1656	}
1657	void rfic :: set_reg_138(){
1658	int reg_138 = (
1659	DischargeTapn_0to3_3 << 4 \|
1660	ChargeTapn16_0to3_3 << 0 );
1661	send_reg(138, reg_138);
1662	}
1663	void rfic :: set_reg_139(){
1664	int reg_139 = (
1665	X1sel_32to39_3 << 0 );
1666	send_reg(139, reg_139);
1667	}
1668	void rfic :: set_reg_140(){
1669	int reg_140 = (
1670	X1sel_40to47_3 << 0 );
1671	send_reg(140, reg_140);
1672	}
1673	void rfic :: set_reg_141(){
1674	int reg_141 = (
1675	X2sel_32to36_3 << 3 );
1676	send_reg(141, reg_141);
1677	}
1678	void rfic :: set_reg_142(){
1679	int reg_142 = (
1680	X2sel_37to41_3 << 3 );
1681	send_reg(142, reg_142);
1682	}
1683	void rfic :: set_reg_143(){
1684	int reg_143 = (
1685	X4sel_32to36_3 << 3 );
1686	send_reg(143, reg_143);
1687	}
1688	void rfic :: set_reg_144(){
1689	int reg_144 = (
1690	X4sel_37to41_3 << 3 );
1691	send_reg(144, reg_144);
1692	}
1693	void rfic :: set_reg_145(){
1694	int reg_145 = (
1695	X8sel_32to36_3 << 3 );
1696	send_reg(145, reg_145);
1697	}
1698	void rfic :: set_reg_146(){
1699	int reg_146 = (
1700	X8sel_41_3 << 7 \|
1701	X8sel_37to40_3 << 3 );
1702	send_reg(146, reg_146);
1703	}
1704	void rfic :: set_reg_147(){
1705	int reg_147 = (
1706	qurx_180Cal_en << 7 \|
1707	qurx_0Cal_en << 6 );
1708	send_reg(147, reg_147);
1709	}
1710	void rfic :: set_reg_152(){
1711	int reg_152 = (
1712	extClkEn << 7 \|
1713	extClkEnBNOTD7 << 6 \|
1714	div2_rst << 5 \|
1715	TxChClkSel << 3 );
1716	send_reg(152, reg_152);
1717	}
1718	void rfic :: set_reg_153(){
1719	int reg_153 = (
1720	TxChClkEn << 5 );
1721	send_reg(153, reg_153);
1722	}
1723	void rfic :: set_reg_156(){
1724	int reg_156 = (
1725	tx_bb_en << 7 \|
1726	tx_bb_fdbk_bw << 5 \|
1727	tx_bb_fdbk_cal_en << 4 \|
1728	tx_bb_fdbk_cart_err_en << 3 \|
1729	tx_bb_fdbk_cart_fb_en << 2 \|
1730	tx_bb_fdbk_cart_fwd_en << 1 );
1731	send_reg(156, reg_156);
1732	}
1733	void rfic :: set_reg_157(){
1734	int reg_157 = (
1735	tx_bb_fdbk_en << 6 \|
1736	tx_bb_fdbk_1q_sel << 5 \|
1737	tx_bb_fdbk_lp << 2 );
1738	send_reg(157, reg_157);
1739	}
1740	void rfic :: set_reg_158(){
1741	int reg_158 = (
1742	tx_bb_fdbk_statt << 5 \|
1743	tx_bb_fdbk_swapi << 4 \|
1744	tx_bb_fdbk_swapq << 3 \|
1745	tx_bb_gain_cmp << 2 );
1746	send_reg(158, reg_158);
1747	}
1748	void rfic :: set_reg_159(){
1749	int reg_159 = (
1750	tx_bb_lp << 5 \|
1751	tx_bb_swapi << 4 \|
1752	tx_bb_swapq << 3 \|
1753	tx_butt_bw << 0 );
1754	send_reg(159, reg_159);
1755	}
1756	void rfic :: set_reg_160(){
1757	int reg_160 = (
1758	tx_bw_trck << 4 \|
1759	tx_cart_en << 3 );
1760	send_reg(160, reg_160);
1761	}
1762	void rfic :: set_reg_161(){
1763	int reg_161 = (
1764	tx_cart_fb_bb_statt << 3 );
1765	send_reg(161, reg_161);
1766	}
1767	void rfic :: set_reg_162(){
1768	int reg_162 = (
1769	tx_cart_fb_dcoc_dac_I1 << 2 );
1770	send_reg(162, reg_162);
1771	}
1772	void rfic :: set_reg_163(){
1773	int reg_163 = (
1774	tx_cart_fb_dcoc_dac_I2 << 2 );
1775	send_reg(163, reg_163);
1776	}
1777	void rfic :: set_reg_164(){
1778	int reg_164 = (
1779	tx_cart_fb_dcoc_dac_Q1 << 2 );
1780	send_reg(164, reg_164);
1781	}
1782	void rfic :: set_reg_165(){
1783	int reg_165 = (
1784	tx_cart_fb_dcoc_dac_Q2 << 2 );
1785	send_reg(165, reg_165);
1786	}
1787	void rfic :: set_reg_166(){
1788	int reg_166 = (
1789	CartesianFeedbackpathDCOCenable << 7 \|
1790	CartesianFeedbackpathenable << 6 \|
1791	CartesianFBpathHiResolutionDCOCenable << 5 \|
1792	CartesianFBpathBW << 1 );
1793	send_reg(166, reg_166);
1794	}
1795	void rfic :: set_reg_167(){
1796	int reg_167 = (
1797	CartesianFBRFGain << 2 );
1798	send_reg(167, reg_167);
1799	}
1800	void rfic :: set_reg_168(){
1801	int reg_168 = (
1802	CartesianFBpathSwapIandIx << 7 \|
1803	CartesianFBpathSwapQandQx << 6 \|
1804	CartesianFBpathSwitchtoforwardSummer << 5 \|
1805	tx_cart_fb_lo_select << 0 );
1806	send_reg(168, reg_168);
1807	}
1808	void rfic :: set_reg_169(){
1809	int reg_169 = (
1810	CartesianFBpathAmp1Gain << 6 \|
1811	CartesianFBpathAmp2Gain << 4 \|
1812	CartesianFBpathAmp3Gain << 2 \|
1813	CartesianFBpathAmp4Gain << 0 );
1814	send_reg(169, reg_169);
1815	}
1816	void rfic :: set_reg_170(){
1817	int reg_170 = (
1818	CartesianFBpathAmpCurrentSelect << 5 \|
1819	CartesianFBpathZeroEnable << 4 \|
1820	tx_cart_zero_statt << 0 );
1821	send_reg(170, reg_170);
1822	}
1823	void rfic :: set_reg_171(){
1824	int reg_171 = (
1825	tx_inbuf_bw << 6 \|
1826	tx_inbuf_statt << 3 );
1827	send_reg(171, reg_171);
1828	}
1829	void rfic :: set_reg_172(){
1830	int reg_172 = (
1831	tx_output_channel_sel << 5 );
1832	send_reg(172, reg_172);
1833	}
1834	void rfic :: set_reg_173(){
1835	int reg_173 = (
1836	tx_p1_bw << 4 \|
1837	tx_pw_bw1 << 2 );
1838	send_reg(173, reg_173);
1839	}
1840	void rfic :: set_reg_174(){
1841	int reg_174 = (
1842	tx_p2_bw2 << 4 \|
1843	PushPullBufferCurrent << 1 );
1844	send_reg(174, reg_174);
1845	}
1846	void rfic :: set_reg_175(){
1847	int reg_175 = (
1848	tx_rf_aoc_bw << 6 \|
1849	RFForwardPathEnable_toMUX << 5 \|
1850	RFForwardPathEnable_ExternalPinenable << 4 \|
1851	tx_rf_fwd_lp << 1 );
1852	send_reg(175, reg_175);
1853	}
1854	void rfic :: set_reg_176(){
1855	int reg_176 = (
1856	tx_rf_fwd_statt1 << 5 \|
1857	tx_rf_fwd_statt2 << 2 );
1858	send_reg(176, reg_176);
1859	}
1860	void rfic :: set_reg_177(){
1861	int reg_177 = (
1862	BBQDivideby2or4Select << 7 \|
1863	BBQQuadGenEnable << 6 \|
1864	BBQPolyphaseQuadGenEnable << 5 );
1865	send_reg(177, reg_177);
1866	}
1867	void rfic :: set_reg_178(){
1868	int reg_178 = (
1869	lofb_tun_s << 4 \|
1870	lofb_tun_sx << 0 );
1871	send_reg(178, reg_178);
1872	}
1873	void rfic :: set_reg_179(){
1874	int reg_179 = (
1875	lofw_tun_s2 << 4 \|
1876	lofw_tun_sx2 << 0 );
1877	send_reg(179, reg_179);
1878	}
1879	void rfic :: set_reg_180(){
1880	int reg_180 = (
1881	reserve_tx26 << 0 );
1882	send_reg(180, reg_180);
1883	}
1884	void rfic :: set_reg_181(){
1885	int reg_181 = (
1886	reserve_tx27 << 0 );
1887	send_reg(181, reg_181);
1888	}
1889	void rfic :: set_reg_192(){
1890	int reg_192 = (
1891	rx_Idac << 3 \|
1892	rx_dcs << 1 \|
1893	rx_den << 0 );
1894	send_reg(192, reg_192);
1895	}
1896	void rfic :: set_reg_193(){
1897	int reg_193 = (
1898	rx_Qdac << 3 \|
1899	rx_cmpen << 1 \|
1900	rx_dcoc << 0 );
1901	send_reg(193, reg_193);
1902	}
1903	void rfic :: set_reg_194(){
1904	int reg_194 = (
1905	rx_ten << 7 \|
1906	rx_ren << 6 \|
1907	rx_dven << 4 \|
1908	rx_dv << 0 );
1909	send_reg(194, reg_194);
1910	}
1911	void rfic :: set_reg_195(){
1912	int reg_195 = (
1913	rx_extc << 7 \|
1914	rx_cen << 4 \|
1915	rx_chck << 2 \|
1916	rx_chcken << 1 \|
1917	rx_fen << 0 );
1918	send_reg(195, reg_195);
1919	}
1920	void rfic :: set_reg_196(){
1921	int reg_196 = (
1922	rx_onchen << 7 \|
1923	rx_offchen << 6 \|
1924	rx_foe << 0 );
1925	send_reg(196, reg_196);
1926	}
1927	void rfic :: set_reg_197(){
1928	int reg_197 = (
1929	rx_offch << 5 \|
1930	rx_onchf << 3 \|
1931	rx_onchc << 1 );
1932	send_reg(197, reg_197);
1933	}
1934	void rfic :: set_reg_198(){
1935	int reg_198 = (
1936	rx_qs << 5 \|
1937	rx_bqg << 3 \|
1938	rx_rq << 0 );
1939	send_reg(198, reg_198);
1940	}
1941	void rfic :: set_reg_199(){
1942	int reg_199 = (
1943	rx_rv << 5 \|
1944	rx_rip << 2 \|
1945	rx_rfp << 0 );
1946	send_reg(199, reg_199);
1947	}
1948	void rfic :: set_reg_200(){
1949	int reg_200 = (
1950	rx_cp_12to8 << 3 \|
1951	rx_gs << 0 );
1952	send_reg(200, reg_200);
1953	}
1954	void rfic :: set_reg_201(){
1955	int reg_201 = (
1956	rx_cp_7to0 << 0 );
1957	send_reg(201, reg_201);
1958	}
1959	void rfic :: set_reg_202(){
1960	int reg_202 = (
1961	rx_cv_10to3 << 0 );
1962	send_reg(202, reg_202);
1963	}
1964	void rfic :: set_reg_203(){
1965	int reg_203 = (
1966	rx_cv_2to0 << 5 \|
1967	rx_cc_2to0 << 2 \|
1968	rx_cq_9to8 << 0 );
1969	send_reg(203, reg_203);
1970	}
1971	void rfic :: set_reg_204(){
1972	int reg_204 = (
1973	rx_cq_7to0 << 0 );
1974	send_reg(204, reg_204);
1975	}
1976
1977
1978	void rfic :: set_reg_206(){
1979	int reg_206 = (
1980	poly_en << 7 );
1981	send_reg(206, reg_206);
1982	}
1983	void rfic :: set_reg_207(){
1984	int reg_207 = (
1985	lorx_tun_s << 4 \|
1986	lorx_tun_sx << 0 );
1987	send_reg(207, reg_207);
1988	}
1989	void rfic :: read_reg_208(){
1990	int reg_208 = get_reg(208);
1991	rx_Icmpo = reg_208 >> 5;
1992	rx_Iodac = reg_208 % 64;
1993	}
1994	void rfic :: read_reg_209(){
1995	int reg_209 = get_reg(209);
1996	rx_Qcmpo = reg_209 >> 5;
1997	rx_Qodac = reg_209 % 64;
1998	}
1999	void rfic :: read_reg_210(){
2000	int reg_210 = get_reg(210);
2001	rx_rc = reg_210;
2002	}
2003	void rfic :: set_reg_220(){
2004	int reg_220 = (
2005	shft_cml_in << 7 \|
2006	vagenable1 << 6 \|
2007	vagenable2 << 5 );
2008	send_reg(220, reg_220);
2009	}
2010	void rfic :: set_reg_222(){
2011	int reg_222 = (
2012	TestMuxBufferEnable << 7 \|
2013	TestMuxEnable << 6 \|
2014	TestMuxSetting << 0 );
2015	send_reg(222, reg_222);
2016	}
2017
2018
2019	bool rfic :: set_rx_gain(float gain){
2020	// Set RX gain
2021	// @param gain){ gain in dB
2022	// Four parameters){ rx_bqg, rx_dcs, rx_gs, rx_rip
2023	// 1 to 39 dB of gain (0 to 38){
2024	// Not all steps available
2025	if (gain < 0.0) gain = 0.0;
2026	if (gain > 38.0)gain = 38.0;
2027
2028	if (gain <= 3){
2029	rx_bqg = 3; //reg 198
2030	rx_dcs = 0; //reg 192
2031	rx_gs = 4; //reg 200
2032	rx_rip = 4; //reg 199
2033	}
2034	else if ( gain >= 3 && gain < 4){
2035	rx_bqg = 3;
2036	rx_dcs = 0;
2037	rx_gs = 4;
2038	rx_rip = 3;
2039	}
2040	else if ( gain >= 4 && gain < 5){
2041	rx_bqg = 3;
2042	rx_dcs = 0;
2043	rx_gs = 2;
2044	rx_rip = 4;
2045	}
2046	else if ( gain >=5 && gain < 6){
2047	rx_bqg = 3;
2048	rx_dcs = 0;
2049	rx_gs = 3;
2050	rx_rip = 3;
2051	}
2052	else if ( gain >= 6 && gain < 7){
2053	rx_bqg = 3;
2054	rx_dcs = 0;
2055	rx_gs = 4;
2056	rx_rip = 2;
2057	}
2058	else if ( gain >= 7 && gain < 8){
2059	rx_bqg = 3;
2060	rx_dcs = 0;
2061	rx_gs = 2;
2062	rx_rip = 3;
2063	}
2064	else if ( gain >= 8 && gain < 9){
2065	rx_bqg = 3;
2066	rx_dcs = 0;
2067	rx_gs = 3;
2068	rx_rip = 2;
2069	}
2070	else if ( gain >= 9 && gain < 10){
2071	rx_bqg = 3;
2072	rx_dcs = 0;
2073	rx_gs = 1;
2074	rx_rip = 3;
2075	}
2076	else if ( gain >= 10 && gain < 11){
2077	rx_bqg = 3;
2078	rx_dcs = 0;
2079	rx_gs = 2;
2080	rx_rip = 2;
2081	}
2082	else if ( gain >= 11 && gain < 12){
2083	rx_bqg = 3;
2084	rx_dcs = 0;
2085	rx_gs = 0;
2086	rx_rip = 3;
2087	}
2088	else if ( gain >= 12 && gain < 13){
2089	rx_bqg = 2;
2090	rx_dcs = 0;
2091	rx_gs = 4;
2092	rx_rip = 2;
2093	}
2094	else if ( gain >= 13 && gain < 14){
2095	rx_bqg = 3;
2096	rx_dcs = 0;
2097	rx_gs = 2;
2098	rx_rip = 1;
2099	}
2100	else if ( gain >= 14 && gain < 15){
2101	rx_bqg = 3;
2102	rx_dcs = 0;
2103	rx_gs = 0;
2104	rx_rip = 2;
2105	}
2106	else if ( gain >= 15 && gain < 16){
2107	rx_bqg = 2;
2108	rx_dcs = 0;
2109	rx_gs = 1;
2110	rx_rip = 3;
2111	}
2112	else if ( gain >= 16 && gain < 17){
2113	rx_bqg = 2;
2114	rx_dcs = 0;
2115	rx_gs = 2;
2116	rx_rip = 2;
2117	}
2118	else if ( gain >= 17 && gain < 18){
2119	rx_bqg = 3;
2120	rx_dcs = 0;
2121	rx_gs = 0;
2122	rx_rip = 2;
2123	}
2124	else if ( gain >= 18 && gain < 19){
2125	rx_bqg = 3;
2126	rx_dcs = 0;
2127	rx_gs = 1;
2128	rx_rip = 0;
2129	}
2130	else if ( gain >= 19 && gain < 20){
2131	rx_bqg = 2;
2132	rx_dcs = 0;
2133	rx_gs = 2;
2134	rx_rip = 1;
2135	}
2136	else if ( gain >= 20 && gain < 21){
2137	rx_bqg = 3;
2138	rx_dcs = 0;
2139	rx_gs = 0;
2140	rx_rip = 0;
2141	}
2142	else if ( gain >= 21 && gain < 22){
2143	rx_bqg = 2;
2144	rx_dcs = 0;
2145	rx_gs = 1;
2146	rx_rip = 1;
2147	}
2148	else if ( gain >= 22 && gain < 23){
2149	rx_bqg = 1;
2150	rx_dcs = 1;
2151	rx_gs = 2;
2152	rx_rip = 2;
2153	}
2154	else if ( gain >= 23 && gain < 24){
2155	rx_bqg = 2;
2156	rx_dcs = 0;
2157	rx_gs = 0;
2158	rx_rip = 1;
2159	}
2160	else if ( gain >= 24 && gain < 25){
2161	rx_bqg = 1;
2162	rx_dcs = 1;
2163	rx_gs = 1;
2164	rx_rip = 2;
2165	}
2166	else if ( gain >= 25 && gain < 26){
2167	rx_bqg = 1;
2168	rx_dcs = 1;
2169	rx_gs = 2;
2170	rx_rip = 1;
2171	}
2172	else if ( gain >= 26 && gain < 27){
2173	rx_bqg = 1;
2174	rx_dcs = 1;
2175	rx_gs = 3;
2176	rx_rip = 0;
2177	}
2178	else if ( gain >= 27 && gain < 28){
2179	rx_bqg = 1;
2180	rx_dcs = 1;
2181	rx_gs = 1;
2182	rx_rip = 1;
2183	}
2184	else if ( gain >= 28 && gain < 29){
2185	rx_bqg = 1;
2186	rx_dcs = 1;
2187	rx_gs = 2;
2188	rx_rip = 0;
2189	}
2190	else if ( gain >= 29 && gain < 30){
2191	rx_bqg = 1;
2192	rx_dcs = 1;
2193	rx_gs = 0;
2194	rx_rip = 1;
2195	}
2196	else if ( gain >= 30 && gain < 31){
2197	rx_bqg = 1;
2198	rx_dcs = 1;
2199	rx_gs = 1;
2200	rx_rip = 0;
2201	}
2202	else if ( gain >= 31 && gain < 32){
2203	rx_bqg = 0;
2204	rx_dcs = 3;
2205	rx_gs = 2;
2206	rx_rip = 1;
2207	}
2208	else if ( gain >= 32 && gain < 33){
2209	rx_bqg = 1;
2210	rx_dcs = 1;
2211	rx_gs = 0;
2212	rx_rip = 0;
2213	}
2214	else if ( gain >= 33 && gain < 34){
2215	rx_bqg = 0;
2216	rx_dcs = 3;
2217	rx_gs = 1;
2218	rx_rip = 1;
2219	}
2220	else if ( gain >= 34 && gain < 35){
2221	rx_bqg = 0;
2222	rx_dcs = 3;
2223	rx_gs = 2;
2224	rx_rip = 0;
2225	}
2226	else if ( gain >= 35 && gain < 36){
2227	rx_bqg = 0;
2228	rx_dcs = 3;
2229	rx_gs = 0;
2230	rx_rip = 1;
2231	}
2232	else if ( gain >= 36 && gain < 38){
2233	rx_bqg = 0;
2234	rx_dcs = 3;
2235	rx_gs = 1;
2236	rx_rip = 0;
2237	}
2238	else if ( gain >= 38){
2239	rx_bqg = 0;
2240	rx_dcs = 3;
2241	rx_gs = 0;
2242	rx_rip = 0;
2243	}
2244	set_reg_198();
2245	set_reg_192();
2246	set_reg_200();
2247	set_reg_199();
2248	return true; //this function always returns true. Maximum gain is 38
2249	}
2250
2251	bool rfic :: set_tx_gain(float gain){
2252	// Set TX gain
2253	// @param gain){ output gain in dB
2254	// Two parameters){
2255	// tx_rf_fwd_statt1, tx_rf_fwd_statt2
2256	// (45 dB of range)
2257	// 5 dB steps
2258	if (gain < 0.0) gain = 0.0;
2259	if (gain > 45.0) gain = 45.0;
2260
2261	if (gain <= 2.5){
2262	tx_rf_fwd_statt1 = 7;
2263	tx_rf_fwd_statt2 = 7;
2264	}
2265	else if ( gain > 2.5 && gain <= 7.5){
2266	tx_rf_fwd_statt1 = 3;
2267	tx_rf_fwd_statt2 = 7;
2268	}
2269	else if ( gain > 7.5 && gain <= 12.5){
2270	tx_rf_fwd_statt1 = 1;
2271	tx_rf_fwd_statt2 = 7;
2272	}
2273	else if ( gain > 12.5 && gain <= 17.5){
2274	tx_rf_fwd_statt1 = 3;
2275	tx_rf_fwd_statt2 = 3;
2276	}
2277	else if ( gain > 17.5 && gain <= 22.5){
2278	tx_rf_fwd_statt1 = 1;
2279	tx_rf_fwd_statt2 = 3;
2280	}
2281	else if ( gain > 22.5 && gain <= 27.5){
2282	tx_rf_fwd_statt1 = 0;
2283	tx_rf_fwd_statt2 = 3;
2284	}
2285	else if ( gain > 27.5 && gain <= 32.5){
2286	tx_rf_fwd_statt1 = 1;
2287	tx_rf_fwd_statt2 = 1;
2288	}
2289	else if ( gain > 32.5 && gain <= 37.5){
2290	tx_rf_fwd_statt1 = 0;
2291	tx_rf_fwd_statt2 = 1;
2292	}
2293	else if ( gain > 37.5 && gain <= 42.5){
2294	tx_rf_fwd_statt1 = 1;
2295	tx_rf_fwd_statt2 = 0;
2296	}
2297	else if ( gain > 42.5){
2298	tx_rf_fwd_statt1 = 0;
2299	tx_rf_fwd_statt2 = 0;
2300	}
2301	set_reg_176();
2302	return true; //this function always returns true. Maximum gain is 45
2303	}
2304	void rfic ::set_fb_gain(float gain){
2305	// Set Feedback path gain
2306	// @param gain){ output gain in dB
2307	// parameters){
2308	// CartesianFBpathAmp1Gain, CartesianFBpathAmp2Gain,
2309	// CartesianFBpathAmp3Gain, CartesianFBpathAmp4Gain
2310	// (40 dB of range)
2311	// 5 dB steps
2312	// FIXME
2313	if (gain < 0.0)gain = 0.0;
2314	if (gain > 40.0) gain = 40.0;
2315
2316	if (gain <= 2.5){
2317	CartesianFBpathAmp1Gain = 3;
2318	CartesianFBpathAmp2Gain = 3;
2319	CartesianFBpathAmp3Gain = 3;
2320	CartesianFBpathAmp4Gain = 3;
2321	}
2322	else if ( gain > 2.5 && gain <= 7.5){
2323	CartesianFBpathAmp1Gain = 3;
2324	CartesianFBpathAmp2Gain = 3;
2325	CartesianFBpathAmp3Gain = 3;
2326	CartesianFBpathAmp4Gain = 1;
2327	}
2328	else if ( gain > 7.5 && gain <= 12.5){
2329	CartesianFBpathAmp1Gain = 3;
2330	CartesianFBpathAmp2Gain = 3;
2331	CartesianFBpathAmp3Gain = 1;
2332	CartesianFBpathAmp4Gain = 1;
2333	}
2334	else if ( gain > 12.5 && gain <= 17.5){
2335	CartesianFBpathAmp1Gain = 3;
2336	CartesianFBpathAmp2Gain = 1;
2337	CartesianFBpathAmp3Gain = 1;
2338	CartesianFBpathAmp4Gain = 1;
2339	}
2340	else if ( gain > 17.5 && gain <= 22.5){
2341	CartesianFBpathAmp1Gain = 1;
2342	CartesianFBpathAmp2Gain = 1;
2343	CartesianFBpathAmp3Gain = 1;
2344	CartesianFBpathAmp4Gain = 1;
2345	}
2346	else if ( gain > 22.5 && gain <= 27.5){
2347	CartesianFBpathAmp1Gain = 1;
2348	CartesianFBpathAmp2Gain = 1;
2349	CartesianFBpathAmp3Gain = 1;
2350	CartesianFBpathAmp4Gain = 0;
2351	}
2352	else if ( gain > 27.5 && gain <= 32.5){
2353	CartesianFBpathAmp1Gain = 1;
2354	CartesianFBpathAmp2Gain = 1;
2355	CartesianFBpathAmp3Gain = 0;
2356	CartesianFBpathAmp4Gain = 0;
2357	}
2358	else if ( gain > 32.5 && gain <= 37.5){
2359	CartesianFBpathAmp1Gain = 1;
2360	CartesianFBpathAmp2Gain = 0;
2361	CartesianFBpathAmp3Gain = 0;
2362	CartesianFBpathAmp4Gain = 0;
2363	}
2364	else if ( gain > 37.5){
2365	CartesianFBpathAmp1Gain = 0;
2366	CartesianFBpathAmp2Gain = 0;
2367	CartesianFBpathAmp3Gain = 0;
2368	CartesianFBpathAmp4Gain = 0;
2369	}
2370	set_reg_169();
2371	}
2372
2373	int* rfic :: calc_freq_vars(double _Fclk,double _Fout){
2374	//
2375	//@param Fclk: Clock frequency of board (Hz)
2376	//@type Fclk: float
2377	//@param Fout: Desired clock frequency for one of three frequency synthesizers (Hz)
2378	//@type Fout: float
2379	//
2380	// Calculate RFIC register variables to set frequency of frequency synthesizers
2381	// data1 corresponds to Ngt, D7, a single bit
2382	// data2 corresponds to NorNdiv4, D6-D0, up to seven bits
2383	// data3 corresponds to RorFrNpRdiv4, up to 26 bits
2384	// D7-D0, D7-D0, D7-D0, D7-D6
2385	// Returns Ngt, NorNdiv4, RorFrNpRdiv4_25to18, RorFrNpRdiv4_17to10,
2386	// RorFrNpRdiv4_9to2, RorFrNpRdiv4_1to0
2387	float NpR;
2388	int data1,data2,data3,temp,Ngt;
2389	int ret_arr[6];
2390	if (_Fout > _Fclk / 4){
2391	NpR = pow(2,-26) * floor(pow(2,26) * _Fclk / _Fout);
2392	data1 = 0;
2393	data2 = int(floor(NpR));
2394	data3 = int(pow(2,26) * (NpR - floor(NpR)));
2395	}
2396	else{
2397	NpR = pow(2,-24)* int(pow(2,24) * _Fclk / _Fout);
2398	data1 = 1;
2399	data2 = int(floor(NpR / 4));
2400	data3 = int(pow(2,26) * (NpR / 4 - floor(NpR / 4)));
2401	}
2402
2403	Ngt = data1;//need to speak to terry about this variable..is this a local variable or supposed to be a class attribute
2404	ret_arr[0]= Ngt;
2405	NorNdiv4 = data2;
2406	ret_arr[1]=NorNdiv4;
2407	RorFrNpRdiv4_25to18 = data3 >> 18;
2408	ret_arr[2]=RorFrNpRdiv4_25to18;
2409	temp = data3 % int(pow(2,18));
2410	RorFrNpRdiv4_17to10 = temp >> 10;
2411	ret_arr[3]= RorFrNpRdiv4_17to10;
2412	temp = data3 % int(pow(2,10));
2413	RorFrNpRdiv4_9to2 = temp >> 2;
2414	ret_arr[4]= RorFrNpRdiv4_9to2;
2415	RorFrNpRdiv4_1to0 = data3 % int(pow(2,2));
2416	ret_arr[5]=RorFrNpRdiv4_1to0;
2417
2418	return ret_arr;
2419	}
2420
2421	int* rfic :: calc_phase_vars(double _Fclk, double _Fout,double phsh){
2422	//
2423	//@param _Fclk: Clock frequency of board (Hz)
2424	//@type _Fclk: float
2425	//@param _Fout: Desired clock frequency for one of three frequency synthesizers (Hz)
2426	//@type _Fout: float
2427	//@param phsh: Desired phase shift in degrees
2428	//@type phsh: float
2429	//
2430	// Calculate RFIC register variables to set phase of frequency synthesizers
2431	// data1 is NGT3_phsh, D7, a single bit
2432	// data2 is NorNdiv4_phsh, D6-D0, up to 7 bits
2433	// data3 is RorFrNpRdiv4_phsh, up to 26 bits
2434	// D7-D0, D7-D0, D7-D0, D7-D6
2435	// Returns Ngt_phsh, NorNdiv4_phsh, RorFrNpRdiv4_25to18_phsh,
2436	// RorFrNpRdiv4_17to10_phsh, RorFrNpRdiv4_9to2_phsh, RorFrNpRdiv4_1to0_phsh
2437
2438	float mod1,tmp,NpR,NpR_ph;
2439	int data1,data2,data3,temp,Ngt_phsh,RorFrNpRdiv4_17to10_phsh,RorFrNpRdiv4_9to2_phsh,RorFrNpRdiv4_25to18_phsh,RorFrNpRdiv4_1to0_phsh;
2440	int ret_arr[6];
2441	if (_Fout <= _Fclk / 4){
2442	mod1 = phsh - 360 * floor(phsh / 360);
2443	NpR = pow(2,-24) * int(pow(2,24) * _Fclk / _Fout);
2444	tmp = (1 + mod1 / 360 / 2) * NpR;
2445	}
2446	else{
2447	mod1 = phsh - 360 * floor(phsh / 360);
2448	NpR = pow(2,-26) * int(pow(2,26) * _Fclk / _Fout);
2449	tmp = (1 + mod1 / 360 / 2) * NpR;
2450	}
2451	if (tmp < 4){
2452	NpR_ph = pow(2,-26) * int(pow(2,26) * (1 + mod1 / 360 / 8) * NpR);
2453	data1 = 0;
2454	data2 = int(floor(NpR_ph));
2455	data3 = int(pow(2,26) * (NpR_ph - floor(NpR_ph)));
2456	}
2457	else if ((tmp >=4) && (tmp < 508)){
2458	NpR_ph = pow(2,-24) * int(pow(2,24) * tmp);
2459	data1 = 1;
2460	data2 = int(floor(NpR_ph / 4));
2461	data3 = int(pow(2,26) * (NpR_ph / 4 - floor(NpR_ph / 4)));
2462	}
2463	else if (tmp >= 508){
2464	NpR_ph = pow(2,-24) * int(pow(2,24) * (1 + (mod1 - 360) / 360 /2) * NpR);
2465	data1 = 1;
2466	data2 = int(floor(NpR_ph / 4));
2467	data3 = int(pow(2,26) * (NpR_ph / 4 - floor(NpR_ph / 4)));
2468	}
2469	Ngt_phsh = data1;
2470	ret_arr[0]=Ngt_phsh;
2471	NorNdiv4_phsh = data2;
2472	ret_arr[1]=NorNdiv4_phsh;
2473	RorFrNpRdiv4_25to18_phsh = data3 >> 18;
2474	ret_arr[2]=RorFrNpRdiv4_25to18_phsh;
2475	temp = data3 % int(pow(2,18));
2476	RorFrNpRdiv4_17to10_phsh = temp >> 10;
2477	ret_arr[3]=RorFrNpRdiv4_17to10_phsh;
2478	temp = data3 % int(pow(2,20));
2479	RorFrNpRdiv4_9to2_phsh = temp >> 2;
2480	ret_arr[4]=RorFrNpRdiv4_9to2_phsh;
2481	RorFrNpRdiv4_1to0_phsh = data3 % 4;
2482	ret_arr[5]=RorFrNpRdiv4_1to0_phsh;
2483
2484	return ret_arr;
2485	}
2486
2487
2488	struct freq_result_t rfic :: set_rx_freq(double target_freq){
2489	//
2490	//@param target_freq: desired receiver frequency in Hz
2491	//@returns (ok, actual_baseb&&_freq) where:
2492	// ok is True or False && indicates success or failure,
2493	// actual_baseb&&_freq is the RF frequency that corresponds to DC in the IF.
2494	//
2495
2496	// Go through Quadrature Generation Initialization Sequence
2497	struct freq_result_t args = {false, 0};
2498	//target_freq = target_freq + 4000000
2499	float try_freq;
2500	if (target_freq <= 500000000){
2501	// Below 500 MHz
2502	std::cout << "Below 500 MHz, divide by 2"<<std::endl;
2503	// Use QuIET frequency divided by 2
2504	// Step 1
2505	X1sel_32to39_3 = 0;
2506	X1sel_40to47_3 = 62;
2507	X2sel_32to36_3 = 0;
2508	X2sel_37to41_3 = 0;
2509	X4sel_32to36_3 = 0;
2510	X4sel_37to41_3 = 0;
2511
2512	set_reg_139();
2513	set_reg_140();
2514	set_reg_141();
2515	set_reg_142();
2516	set_reg_143();
2517	set_reg_144();
2518
2519	// Step 2
2520	X1sel_40to47_3 = 63;
2521
2522	set_reg_140();
2523
2524	try_freq = target_freq * 2;
2525
2526	}
2527	else if ((target_freq > 500000000) && (target_freq <= 1000000000)){
2528	// Between 500 MHz && 1 GHz
2529	std::cout << "Between 500 MHz and 1 GHz"<<std::endl;
2530	// Use QuIET frequency
2531	// Step 1
2532	X1sel_32to39_3 = 1;
2533	X1sel_40to47_3 = 192;
2534	X2sel_32to36_3 = 0;
2535	X2sel_37to41_3 = 0;
2536	X4sel_32to36_3 = 0;
2537	X4sel_37to41_3 = 0;
2538
2539	set_reg_139();
2540	set_reg_140();
2541	set_reg_141();
2542	set_reg_142();
2543	set_reg_143();
2544	set_reg_144();
2545
2546	// Step 2
2547	X1sel_32to39_3 = 73;
2548
2549	set_reg_139();
2550
2551	// Step 3
2552	X1sel_32to39_3 = 201;
2553
2554	set_reg_139();
2555
2556	try_freq = target_freq;
2557
2558	// Set Quadrature Generator Charge/Discharge Taps
2559	DischargeTap16_0to3_3 = 6;
2560	ChargeTap16_0to3_3 = 7;
2561	DischargeTapn_0to3_3 = 0;
2562	ChargeTapn16_0to3_3 = 5;
2563
2564	// Set Quadrature Generator Delays
2565	Qg00degDelay_0to4_3 = 16;
2566	Qg90degDelay_0to4_3 = 31;
2567	Qg180degDelay_0to4_3 = 0;
2568	Qg270degDelay_0to4_3 = 31;
2569
2570	set_reg_133();
2571	set_reg_134();
2572	set_reg_135();
2573	set_reg_136();
2574	set_reg_137();
2575	set_reg_138();
2576	}
2577
2578	else if ((target_freq > 1000000000) && (target_freq <= 2000000000)){
2579	// Between 1 GHz && 2 GHz
2580	std::cout << "Between 1 GHz and 2 GHz, multiply by 2"<< std::endl;
2581	// Use QuIET multiplied by 2
2582	// Step 1
2583	X1sel_32to39_3 = 0;
2584	X1sel_40to47_3 = 0;
2585	X2sel_32to36_3 = 0;
2586	X2sel_37to41_3 = 7;
2587	X4sel_32to36_3 = 0;
2588	X4sel_37to41_3 = 0;
2589
2590	set_reg_139();
2591	set_reg_140();
2592	set_reg_141();
2593	set_reg_142();
2594	set_reg_143();
2595	set_reg_144();
2596
2597	// Step 2
2598	X2sel_32to36_3 = 9;
2599
2600	set_reg_141();
2601
2602	// Step 3
2603	X2sel_32to36_3 = 25;
2604
2605	set_reg_141();
2606
2607	// Step 4
2608	X2sel_32to36_3 = 16;
2609
2610	set_reg_141();
2611
2612	try_freq = target_freq / 2;
2613
2614	// Set Quadrature Generator Charge/Discharge Taps
2615	DischargeTap16_0to3_3 = 9;
2616	ChargeTap16_0to3_3 = 3;
2617	DischargeTapn_0to3_3 = 3;
2618	ChargeTapn16_0to3_3 = 5;
2619
2620	// Set Quadrature Generator Delays
2621	Qg00degDelay_0to4_3 = 31;
2622	Qg90degDelay_0to4_3 = 31;
2623	Qg180degDelay_0to4_3 = 0;
2624	Qg270degDelay_0to4_3 = 31;
2625
2626	set_reg_133();
2627	set_reg_134();
2628	set_reg_135();
2629	set_reg_136();
2630	set_reg_137();
2631	set_reg_138();
2632	}
2633
2634	else if ((target_freq > 2000000000.0) && (target_freq <= 4000000000.0)){
2635	// 2 to 4 GHz
2636	std::cout<< "From 2 to 4 GHz, multiply by 4"<<std::endl;
2637	// Use QuIET frequency multiplied by 4
2638	// Step 1
2639	X1sel_32to39_3 = 0;
2640	X1sel_40to47_3 = 0;
2641	X2sel_32to36_3 = 0;
2642	X2sel_37to41_3 = 0;
2643	X4sel_32to36_3 = 0;
2644	X4sel_37to41_3 = 7;
2645
2646	set_reg_139();
2647	set_reg_140();
2648	set_reg_141();
2649	set_reg_142();
2650	set_reg_143();
2651	set_reg_144();
2652
2653	// Step 2
2654	X4sel_32to36_3 = 9;
2655
2656	set_reg_143();
2657
2658	// Step 3
2659	X4sel_32to36_3 = 25;
2660
2661	set_reg_143();
2662
2663	try_freq = target_freq / 4;
2664
2665	// Set Quadrature Generator Charge/Discharge Taps
2666	DischargeTap16_0to3_3 = 16;
2667	ChargeTap16_0to3_3 = 0;
2668	DischargeTapn_0to3_3 = 7;
2669	ChargeTapn16_0to3_3 = 7;
2670
2671	// Set Quadrature Generator Delays
2672	Qg00degDelay_0to4_3 = 0;
2673	Qg90degDelay_0to4_3 = 31;
2674	Qg180degDelay_0to4_3 = 0;
2675	Qg270degDelay_0to4_3 = 31;
2676
2677	set_reg_133();
2678	set_reg_134();
2679	set_reg_135();
2680	set_reg_136();
2681	set_reg_137();
2682	set_reg_138();
2683	}
2684
2685	else if (target_freq > 4000000000.0){
2686	// Above 4 GHz, doesn't work
2687	args.ok = false;
2688	args.baseband_freq = target_freq;
2689	return args;
2690	}
2691	// FIXME
2692	/*// Above 4 GHz
2693	std::cout<< "Above 4 GHz, multiply by 8"<<std::endl;
2694	// Use QuIET frequency multiplied by 8
2695	// Step 1
2696	X1sel_32to39_3 = 0;
2697	X1sel_40to47_3 = 0;
2698	X2sel_32to36_3 = 0;
2699	X2sel_37to41_3 = 0;
2700	X4sel_32to36_3 = 0;
2701	X4sel_37to41_3 = 0;
2702	X8sel_32to36_3 = 0;
2703	X8sel_41_3 = 0;
2704	X8sel_37to40_3 = 7;
2705
2706	set_reg_139();
2707	set_reg_140();
2708	set_reg_141();
2709	set_reg_142();
2710	set_reg_143();
2711	set_reg_144();
2712	set_reg_145();
2713	set_reg_146();
2714
2715	// Step 2
2716	X8sel_32to36_3 = 9;
2717
2718	set_reg_145();
2719
2720	// Step 3
2721	X8sel_32to36_3 = 25;
2722
2723	set_reg_145();
2724
2725	try_freq = target_freq / 8;
2726
2727	// Set Quadrature Generator Charge/Discharge Taps
2728	ChargeTap16_0to3_3 = 15;
2729	ChargeTapn16_0to3_3 = 15;
2730
2731	DischargeTap16_0to3_3 = 6;
2732	DischargeTapn16_0to3_3 = 4;
2733
2734	set_reg_137();
2735	set_reg_138();*/
2736
2737
2738	Foutrx = target_freq;
2739	int * ret_arr;
2740	ret_arr= calc_freq_vars(Fclk, try_freq);
2741	Ngt3_3 = ret_arr[0];
2742	NorNdiv4_3= ret_arr[1];
2743	RorFrNpRdiv4_25to18_3= ret_arr[2];
2744	RorFrNpRdiv4_17to10_3= ret_arr[3];
2745	RorFrNpRdiv4_9to2_3= ret_arr[4];
2746	RorFrNpRdiv4_1to0_3= ret_arr[5];
2747
2748	set_reg_104();
2749	set_reg_105();
2750	set_reg_106();
2751	set_reg_107();
2752	set_reg_108();
2753
2754	args.ok = true;
2755	args.baseband_freq = target_freq;
2756	return args;
2757	//FIXME -- How do I know if the RFIC successfully attained the desired frequency?//
2758
2759	}
2760
2761	struct freq_result_t rfic :: set_tx_freq(double target_freq){
2762	//
2763	//@param target_freq: desired transmitter frequency in Hz
2764	//@returns (ok, actual_baseb&&_freq) where:
2765	// ok is True or False && indicates success or failure,
2766	// actual_baseb&&_freq is the RF frequency that corresponds to DC in the IF.
2767	//
2768
2769	// Go through Quadrature Generation Initialization Sequence
2770
2771	// FIXME
2772	//target_freq = target_freq + 4000000
2773	//target_freq = target_freq + 1000000
2774
2775	struct freq_result_t args = {false, 0};
2776
2777	double try_freq;
2778	if (target_freq <= 500000000.0){
2779	std::cout<< "Below 500 MHz, divide by 2"<<std::endl;
2780	// Use QuIET frequency divided by 2
2781	// Step 1
2782	X1sel_32to39 = 0;
2783	X1sel_40to47 = 62;
2784	X2sel_32to36 = 0;
2785	X2sel_37to41 = 0;
2786	X4sel_32to36 = 0;
2787	X4sel_37to41 = 0;
2788
2789	set_reg_35();
2790	set_reg_36();
2791	set_reg_37();
2792	set_reg_38();
2793	set_reg_39();
2794	set_reg_40();
2795
2796	// Step 2
2797	X1sel_40to47 = 63;
2798
2799	set_reg_36();
2800
2801	try_freq = target_freq * 2;
2802	}
2803	else if ((target_freq > 500000000.0) && (target_freq <= 1000000000.0)){
2804	std::cout<< "Between 500 MHz and 1 GHz"<<std::endl;
2805	// Use QuIET frequency
2806	// Step 1
2807	X1sel_32to39 = 1;
2808	X1sel_40to47 = 192;
2809	X2sel_32to36 = 0;
2810	X2sel_37to41 = 0;
2811	X4sel_32to36 = 0;
2812	X4sel_37to41 = 0;
2813
2814	set_reg_35();
2815	set_reg_36();
2816	set_reg_37();
2817	set_reg_38();
2818	set_reg_39();
2819	set_reg_40();
2820
2821	// Step 2
2822	X1sel_32to39 = 73;
2823
2824	set_reg_35();
2825
2826	// Step 3
2827	X1sel_32to39 = 201;
2828
2829	set_reg_35();
2830
2831	try_freq = target_freq;
2832
2833	// Set Quadrature Generator Charge/Discharge Taps && Delays
2834	Qg00degDelay_0to4 = 15;
2835	Qg90degDelay_0to4 = 12;
2836	Qg180degDelay_0to4 = 3;
2837	Qg270degDelay_0to4 = 12;
2838
2839	set_reg_29();
2840	set_reg_30();
2841	set_reg_31();
2842	set_reg_32();
2843
2844	DischargeTap16_0to3 = 1;
2845	ChargeTap16_0to3 = 8;
2846	DischargeTapn_0to3 = 7;
2847	ChargeTapn16_0to3 = 0;
2848
2849	set_reg_33();
2850	set_reg_34();
2851	}
2852	else if ((target_freq > 1000000000.0) && (target_freq <= 2000000000.0)){
2853	std::cout<<"Between 1 GHz and 2 GHz, multiply by 2"<<std::endl;
2854	// Use QuIET multiplied by 2
2855	// Step 1
2856	X1sel_32to39 = 0;
2857	X1sel_40to47 = 0;
2858	X2sel_32to36 = 0;
2859	X2sel_37to41 = 7;
2860	X4sel_32to36 = 0;
2861	X4sel_37to41 = 0;
2862
2863	set_reg_35();
2864	set_reg_36();
2865	set_reg_37();
2866	set_reg_38();
2867	set_reg_39();
2868	set_reg_40();
2869
2870	// Step 2
2871	X2sel_32to36 = 9;
2872
2873	set_reg_37();
2874
2875	// Step 3
2876	X2sel_32to36 = 25;
2877
2878	set_reg_37();
2879
2880	// Step 4
2881	//X2sel_32to36 = 16;
2882
2883	//set_reg_37();
2884
2885	try_freq = target_freq / 2;
2886
2887	// Set Quadrature Generator Charge/Discharge Taps && Delays
2888	Qg00degDelay_0to4 = 7;
2889	Qg90degDelay_0to4 = 8;
2890	Qg180degDelay_0to4 = 7;
2891	Qg270degDelay_0to4 = 5;
2892
2893	set_reg_29();
2894	set_reg_30();
2895	set_reg_31();
2896	set_reg_32();
2897
2898	DischargeTap16_0to3 = 1;
2899	ChargeTap16_0to3 = 13;
2900
2901	DischargeTapn_0to3 = 3;
2902	ChargeTapn16_0to3 = 9;
2903
2904	set_reg_33();
2905	set_reg_34();
2906	}
2907	else if ((target_freq > 2000000000.0) && (target_freq <= 4000000000.0)){
2908	std::cout<<"2-4 GHz, multiply by 4"<<std::endl;
2909	// Use QuIET frequency multiplied by 4
2910	// Step 1
2911	X1sel_32to39 = 0;
2912	X1sel_40to47 = 0;
2913	X2sel_32to36 = 0;
2914	X2sel_37to41 = 0;
2915	X4sel_32to36 = 0;
2916	X4sel_37to41 = 7;
2917
2918	set_reg_35();
2919	set_reg_36();
2920	set_reg_37();
2921	set_reg_38();
2922	set_reg_39();
2923	set_reg_40();
2924
2925	// Step 2
2926	X4sel_32to36 = 9;
2927
2928	set_reg_39();
2929
2930	// Step 3
2931	X4sel_32to36 = 25;
2932
2933	set_reg_39();
2934
2935	try_freq = target_freq / 4;
2936
2937	// Set Quadrature Generator Charge/Discharge Taps && Delays
2938	Qg00degDelay_0to4 = 0;
2939	Qg90degDelay_0to4 = 17;
2940	Qg180degDelay_0to4 = 15;
2941	Qg270degDelay_0to4 = 20;
2942
2943	set_reg_29();
2944	set_reg_30();
2945	set_reg_31();
2946	set_reg_32();
2947
2948	DischargeTap16_0to3 = 15;
2949	ChargeTap16_0to3 = 0;
2950
2951	DischargeTapn_0to3 = 10;
2952	ChargeTapn16_0to3 = 8;
2953
2954	set_reg_33();
2955	set_reg_34();
2956	}
2957	else if (target_freq > 4000000000.0){
2958	// Above 4 GHz, doesn't work
2959	args.ok = false;
2960	args.baseband_freq = target_freq;
2961	return args;
2962	}
2963
2964	Fouttx = target_freq;
2965
2966	int * ret_arr;
2967	ret_arr= calc_freq_vars(Fclk, try_freq);
2968	Ngt3 = ret_arr[0];
2969	NorNdiv4= ret_arr[1];
2970	RorFrNpRdiv4_25to18= ret_arr[2];
2971	RorFrNpRdiv4_17to10= ret_arr[3];
2972	RorFrNpRdiv4_9to2= ret_arr[4];
2973	RorFrNpRdiv4_1to0= ret_arr[5];
2974
2975	set_reg_0();
2976	set_reg_1();
2977	set_reg_2();
2978	set_reg_3();
2979	set_reg_4();
2980
2981	args.ok = true;
2982	args.baseband_freq = target_freq;
2983	return args;
2984	//FIXME -- How do I know if the RFIC successfully attained the desired frequency?//
2985
2986	}
2987
2988	bool rfic :: set_fb_freq(double target_freq){
2989	//
2990	//@param target_freq: desired transmitter frequency in Hz
2991	//@returns (ok, actual_baseb&&_freq) where:
2992	// ok is True or False && indicates success or failure,
2993	// actual_baseb&&_freq is the RF frequency that corresponds to DC in the IF.
2994	//
2995
2996	// Go through Quadrature Generation Initialization Sequence
2997	double try_freq;
2998	if (target_freq <= 500000000.0){
2999	std::cout<<"Below 500 MHz, divide by 2"<<std::endl;
3000	// Use QuIET frequency divided by 2
3001	// Step 1
3002	X1sel_32to39_2 = 0;
3003	X1sel_40to47_2 = 62;
3004	X2sel_32to36_2 = 0;
3005	X2sel_37to41_2 = 0;
3006	X4sel_32to36_2 = 0;
3007	X4sel_37to41_2 = 0;
3008
3009	set_reg_83();
3010	set_reg_84();
3011	set_reg_85();
3012	set_reg_86();
3013	set_reg_87();
3014	set_reg_88();
3015
3016	// Step 2
3017	X1sel_40to47_2 = 63;
3018
3019	set_reg_84();
3020
3021	try_freq = target_freq * 2;
3022	}
3023	else if ((target_freq > 500000000) && (target_freq <= 1000000000)){
3024	std::cout<< "Between 500 MHz and 1 GHz"<<std::endl;
3025	// Use QuIET frequency
3026	// Step 1
3027	X1sel_32to39_2 = 1;
3028	X1sel_40to47_2 = 192;
3029	X2sel_32to36_2 = 0;
3030	X2sel_37to41_2 = 0;
3031	X4sel_32to36_2 = 0;
3032	X4sel_37to41_2 = 0;
3033
3034	set_reg_83();
3035	set_reg_84();
3036	set_reg_85();
3037	set_reg_86();
3038	set_reg_87();
3039	set_reg_88();
3040
3041	// Step 2
3042	X1sel_32to39_2 = 73;
3043
3044	set_reg_83();
3045
3046	// Step 3
3047	X1sel_32to39_2 = 201;
3048
3049	set_reg_83();
3050
3051	try_freq = target_freq;
3052
3053	// Set Quadrature Generator Charge/Discharge Taps
3054	// FIXME
3055	//ChargeTap16_0to3_2 = 7;
3056	//ChargeTapn16_0to3_2 = 5;
3057
3058	//DischargeTap16_0to3_2 = 6;
3059	//DischargeTapn16_0to3_2 = 0;
3060
3061	//set_reg_81();
3062	//set_reg_82();
3063	}
3064
3065	else if ((target_freq > 1000000000) && (target_freq <= 2000000000)){
3066	std::cout<<"Between 1 GHz and 2 GHz, multiply by 2"<<std::endl;
3067	// Use QuIET multiplied by 2
3068	// Step 1
3069	X1sel_32to39_2 = 0;
3070	X1sel_40to47_2 = 0;
3071	X2sel_32to36_2 = 0;
3072	X2sel_37to41_2 = 7;
3073	X4sel_32to36_2 = 0;
3074	X4sel_37to41_2 = 0;
3075
3076	set_reg_83();
3077	set_reg_84();
3078	set_reg_85();
3079	set_reg_86();
3080	set_reg_87();
3081	set_reg_88();
3082
3083	// Step 2
3084	X2sel_32to36_2 = 9;
3085
3086	set_reg_85();
3087
3088	// Step 3
3089	X2sel_32to36_2 = 25;
3090
3091	// Step 4
3092	//X2sel_32to36 = 16;
3093
3094	set_reg_85();
3095
3096	try_freq = target_freq / 2;
3097
3098	// Set Quadrature Generator Charge/Discharge Taps
3099	// FIXME
3100	//ChargeTap16_0to3_2 = 7;
3101	//ChargeTapn16_0to3_2 = 8;
3102
3103	//DischargeTap16_0to3_2 = 15;
3104	//DischargeTapn16_0to3_2 = 15;
3105
3106	//set_reg_81();
3107	//set_reg_82();
3108	}
3109	else if ((target_freq > 2000000000.0) && (target_freq <= 4000000000.0)){
3110	std::cout<<"2-4 GHz, multiply by 4"<<std::endl;
3111	// Use QuIET frequency multiplied by 4
3112	// Step 1
3113	X1sel_32to39_2 = 0;
3114	X1sel_40to47_2 = 0;
3115	X2sel_32to36_2 = 0;
3116	X2sel_37to41_2 = 0;
3117	X4sel_32to36_2 = 0;
3118	X4sel_37to41_2 = 7;
3119
3120	set_reg_83();
3121	set_reg_84();
3122	set_reg_85();
3123	set_reg_86();
3124	set_reg_87();
3125	set_reg_88();
3126
3127	// Step 2
3128	X4sel_32to36_2 = 9;
3129
3130	set_reg_87();
3131
3132	// Step 3
3133	X4sel_32to36_2 = 25;
3134
3135	set_reg_87();
3136
3137	try_freq = target_freq / 4;
3138
3139	// Set Quadrature Generator Charge/Discharge Taps
3140	// FIXME
3141	//ChargeTap16_0to3_2 = 15;
3142	//ChargeTapn16_0to3_2 = 15;
3143
3144	//DischargeTap16_0to3_2 = 6;
3145	//DischargeTapn16_0to3_2 = 4;
3146
3147	//set_reg_81();
3148	//set_reg_82();
3149	}
3150	else if (target_freq > 4000000000.0){
3151	// Above 4 GHz, doesn't work
3152	return false;
3153	}
3154	Foutfb = target_freq;
3155	int * ret_arr;
3156	ret_arr= calc_freq_vars(Fclk, try_freq);
3157	Ngt3_2 = ret_arr[0];
3158	NorNdiv4_2= ret_arr[1];
3159	RorFrNpRdiv4_25to18_2= ret_arr[2];
3160	RorFrNpRdiv4_17to10_2= ret_arr[3];
3161	RorFrNpRdiv4_9to2_2= ret_arr[4];
3162	RorFrNpRdiv4_1to0_2= ret_arr[5];
3163
3164
3165	set_reg_48();
3166	set_reg_49();
3167	set_reg_50();
3168	set_reg_51();
3169	set_reg_52();
3170
3171	return true;
3172	//FIXME -- How do I know if the RFIC successfully attained the desired frequency?//
3173	}
3174
3175	/////////////////////////////////////////
3176
3177	bool rfic :: set_rx_phase(int phsh){
3178	//
3179	//@param phsh{ desired phase shift in degrees
3180	//@returns (ok) where{
3181	// ok is True or False and indicates success or failure
3182	//
3183	double synth_freq;
3184	phsh = phsh % 360;
3185
3186	if (Foutrx <= 500000000.0)
3187	synth_freq = Foutrx * 2;
3188	else if ( (Foutrx > 500000000.0) and (Foutrx <= 1000000000.0))
3189	synth_freq = Foutrx;
3190	else if ( (Foutrx > 1000000000.0) and (Foutrx < 2000000000.0))
3191	synth_freq = Foutrx / 2;
3192	else if (Foutrx > 2000000000.0)
3193	synth_freq = Foutrx / 4;
3194
3195	int * ret_arr;
3196	ret_arr= calc_phase_vars(Fclk, synth_freq,phsh);
3197	Qu_tx_Ngt3_3 = ret_arr[0];
3198	NorNdiv4_phsh_3= ret_arr[1];
3199	RorFrNpRdiv4_phsh_25to18_3= ret_arr[2];
3200	RorFrNpRdiv4_phsh_17to10_3= ret_arr[3];
3201	RorFrNpRdiv4_phsh_9to2_3= ret_arr[4];
3202	RorFrNpRdiv4_phsh_1to0_3= ret_arr[5];
3203
3204
3205	set_reg_109();
3206	set_reg_110();
3207	set_reg_111();
3208	set_reg_112();
3209	set_reg_113();
3210
3211	return true;
3212	//FIXME -- How do I know if the RFIC successfully attained the desired phase?//
3213	}
3214
3215	bool rfic :: set_tx_phase(int phsh){
3216	//
3217	//@param phsh{ desired phase shift in degrees
3218	//@returns (ok) where{
3219	// ok is True or False and indicates success or failure
3220	//
3221	double synth_freq;
3222	phsh = phsh % 360;
3223
3224	if (Fouttx <= 500000000.0)
3225	synth_freq = Fouttx * 2;
3226	else if ( (Fouttx > 500000000.0) and (Fouttx <= 1000000000.0))
3227	synth_freq = Fouttx;
3228	else if ( (Fouttx > 1000000000.0) and (Fouttx < 2000000000.0))
3229	synth_freq = Fouttx / 2;
3230	else if (Fouttx > 2000000000)
3231	synth_freq = Fouttx / 4;
3232
3233	int * ret_arr;
3234	ret_arr= calc_phase_vars(Fclk, synth_freq,phsh);
3235	Qu_tx_Ngt3_3 = ret_arr[0];
3236	NorNdiv4_phsh_3= ret_arr[1];
3237	RorFrNpRdiv4_phsh_25to18_3= ret_arr[2];
3238	RorFrNpRdiv4_phsh_17to10_3= ret_arr[3];
3239	RorFrNpRdiv4_phsh_9to2_3= ret_arr[4];
3240	RorFrNpRdiv4_phsh_1to0_3= ret_arr[5];
3241
3242	set_reg_5();
3243	set_reg_6();
3244	set_reg_7();
3245	set_reg_8();
3246	set_reg_9();
3247
3248	//FIXME -- How do I know if the RFIC successfully attained the desired phase?//
3249	return true;
3250	}
3251
3252	bool rfic :: set_fb_phase(int phsh){
3253	//
3254	//@param phsh{ desired phase shift in degrees
3255	//@returns (ok) where{
3256	// ok is True or False and indicates success or failure
3257	//
3258	double synth_freq;
3259	phsh = phsh % 360;
3260
3261	if (Foutfb <= 500000000.0)
3262	synth_freq = Foutfb * 2;
3263	else if ( (Foutfb > 500000000.0) and (Foutfb <= 1000000000.0))
3264	synth_freq = Foutfb;
3265	else if ( (Foutfb > 1000000000.0) and (Foutfb < 2000000000.0))
3266	synth_freq = Foutfb / 2;
3267	else if (Foutfb > 2000000000.0)
3268	synth_freq = Foutfb / 4;
3269
3270
3271	int * ret_arr;
3272	ret_arr= calc_phase_vars(Fclk, synth_freq,phsh);
3273	Qu_tx_Ngt3_3 = ret_arr[0];
3274	NorNdiv4_phsh_3= ret_arr[1];
3275	RorFrNpRdiv4_phsh_25to18_3= ret_arr[2];
3276	RorFrNpRdiv4_phsh_17to10_3= ret_arr[3];
3277	RorFrNpRdiv4_phsh_9to2_3= ret_arr[4];
3278	RorFrNpRdiv4_phsh_1to0_3= ret_arr[5];
3279
3280	set_reg_53();
3281	set_reg_54();
3282	set_reg_55();
3283	set_reg_56();
3284	set_reg_57();
3285
3286	//FIXME -- How do I know if the RFIC successfully attained the desired phase?//
3287	return true;
3288	}
3289
3290	bool rfic :: set_rx_bw(float bw){
3291	//
3292	//@param bw{ desired bandwidth in Hz
3293	//
3294	// Available bandwidth{ 4.25 kHz to 14 MHz (baseband)
3295	// FIXME
3296	std::cout<<"Desired bandwidth :"<< bw<<std::endl;
3297	if (bw <= 5250){
3298	// Set BW to 3.532 kHz
3299	rx_rfp = 3;
3300	rx_cp_12to8 = 31;
3301	rx_cp_7to0 = 240;
3302
3303	rx_rv = 7;
3304	rx_cv_10to3 = 254;
3305	rx_cv_2to0 = 0;
3306
3307	rx_rq = 7;
3308	rx_cq_9to8 = 3;
3309	rx_cq_7to0 = 240;
3310	}
3311
3312	else if (bw > 5250 and bw <= 10500){
3313	// Set BW to 7.065 kHz
3314	rx_rfp = 3;
3315	rx_cp_12to8 = 31;
3316	rx_cp_7to0 = 240;
3317
3318	rx_rv = 5;
3319	rx_cv_10to3 = 254;
3320	rx_cv_2to0 = 0;
3321
3322	rx_rq = 5;
3323	rx_cq_9to8 = 3;
3324	rx_cq_7to0 = 240;
3325	}
3326	else if (bw > 10500 and bw <= 21000){
3327	// Set BW to 14.130 kHz
3328	rx_rfp = 2;
3329	rx_cp_12to8 = 31;
3330	rx_cp_7to0 = 240;
3331
3332	rx_rv = 4;
3333	rx_cv_10to3 = 254;
3334	rx_cv_2to0 = 0;
3335
3336	rx_rq = 4;
3337	rx_cq_9to8 = 3;
3338	rx_cq_7to0 = 240;
3339	}
3340
3341	else if (bw > 21000 and bw <= 42000){
3342	// Set BW to 28.259 kHz
3343	rx_rfp = 2;
3344	rx_cp_12to8 = 15;
3345	rx_cp_7to0 = 240;
3346
3347	rx_rv = 3;
3348	rx_cv_10to3 = 254;
3349	rx_cv_2to0 = 0;
3350
3351	rx_rq = 3;
3352	rx_cq_9to8 = 3;
3353	rx_cq_7to0 = 240;
3354	}
3355	else if (bw > 42000 and bw <= 84500){
3356	// Set BW to 56.518 kHz
3357	rx_rfp = 2;
3358	rx_cp_12to8 = 7;
3359	rx_cp_7to0 = 240;
3360
3361	rx_rv = 2;
3362	rx_cv_10to3 = 254;
3363	rx_cv_2to0 = 0;
3364
3365	rx_rq = 2;
3366	rx_cq_9to8 = 3;
3367	rx_cq_7to0 = 240;
3368	}
3369	else if (bw > 84500 and bw <= 169500){
3370	// Set BW to 113.036 kHz
3371	rx_rfp = 2;
3372	rx_cp_12to8 = 3;
3373	rx_cp_7to0 = 240;
3374
3375	rx_rv = 1;
3376	rx_cv_10to3 = 254;
3377	rx_cv_2to0 = 0;
3378
3379	rx_rq = 1;
3380	rx_cq_9to8 = 3;
3381	rx_cq_7to0 = 240;
3382	}
3383	else if (bw > 169500 and bw <= 339000){
3384	// Set BW to 226.072 kHz
3385	rx_rfp = 2;
3386	rx_cp_12to8 = 1;
3387	rx_cp_7to0 = 240;
3388
3389	rx_rv = 1;
3390	rx_cv_10to3 = 126;
3391	rx_cv_2to0 = 0;
3392
3393	rx_rq = 1;
3394	rx_cq_9to8 = 1;
3395	rx_cq_7to0 = 240;
3396	}
3397	else if (bw > 339000 and bw <= 667000){
3398	// Set BW to 452.145 kHz
3399	rx_rfp = 1;
3400	rx_cp_12to8 = 1;
3401	rx_cp_7to0 = 240;
3402
3403	rx_rv = 0;
3404	rx_cv_10to3 = 254;
3405	rx_cv_2to0 = 0;
3406
3407	rx_rq = 1;
3408	rx_cq_9to8 = 0;
3409	rx_cq_7to0 = 240;
3410	}
3411	else if (bw > 667000 and bw <= 1356000){
3412	// Set BW to 904.289 kHz
3413	rx_rfp = 1;
3414	rx_cp_12to8 = 0;
3415	rx_cp_7to0 = 240;
3416
3417	rx_rv = 0;
3418	rx_cv_10to3 = 126;
3419	rx_cv_2to0 = 0;
3420
3421	rx_rq = 0;
3422	rx_cq_9to8 = 3;
3423	rx_cq_7to0 = 240;
3424	}
3425	else if (bw > 1356000 and bw <= 2712500){
3426	// Set BW to 1808.579 kHz
3427	rx_rfp = 1;
3428	rx_cp_12to8 = 0;
3429	rx_cp_7to0 = 112;
3430
3431	rx_rv = 0;
3432	rx_cv_10to3 = 62;
3433	rx_cv_2to0 = 0;
3434
3435	rx_rq = 0;
3436	rx_cq_9to8 = 1;
3437	rx_cq_7to0 = 240;
3438	}
3439	else if (bw > 2712500 and bw <= 5425500){
3440	// Set BW to 3617.157 kHz
3441	rx_rfp = 0;
3442	rx_cp_12to8 = 0;
3443	rx_cp_7to0 = 112;
3444
3445	rx_rv = 0;
3446	rx_cv_10to3 = 30;
3447	rx_cv_2to0 = 0;
3448
3449	rx_rq = 0;
3450	rx_cq_9to8 = 0;
3451	rx_cq_7to0 = 240;
3452	}
3453	else if (bw > 5425500 and bw <= 10851000){
3454	// Set BW to 7234.315 kHz
3455	rx_rfp = 0;
3456	rx_cp_12to8 = 0;
3457	rx_cp_7to0 = 48;
3458
3459	rx_rv = 0;
3460	rx_cv_10to3 = 14;
3461	rx_cv_2to0 = 0;
3462
3463	rx_rq = 0;
3464	rx_cq_9to8 = 0;
3465	rx_cq_7to0 = 112;
3466	}
3467	else if (bw > 10851000){
3468	// Set BW to 14468.630 kHz
3469	rx_rfp = 0;
3470	rx_cp_12to8 = 0;
3471	rx_cp_7to0 = 16;
3472
3473	rx_rv = 0;
3474	rx_cv_10to3 = 6;
3475	rx_cv_2to0 = 0;
3476
3477	rx_rq = 0;
3478	rx_cq_9to8 = 0;
3479	rx_cq_7to0 = 48;
3480	}
3481	set_reg_198();
3482	set_reg_199();
3483	set_reg_200();
3484	set_reg_201();
3485	set_reg_202();
3486	set_reg_203();
3487	set_reg_204();
3488	return true; //always returning true..may have to change this
3489
3490	}
3491
3492
3493
3494	bool rfic :: set_tx_bw(float bw){
3495	//
3496	//@param bw{ desired bandwidth in Hz
3497	//
3498	// Available bandwidth{ 6.25 kHz to 14+ MHz (baseband)
3499	// FIXME
3500	std::cout<<"Desired bandwidth :"<< bw<<std::endl;
3501	if (bw <= 20000){
3502	// Set BW to 12.5 kHz
3503	tx_p1_bw = 3;
3504	tx_p2_bw2 = 15;
3505	}
3506	else if (bw > 20000 and bw <= 37500){
3507	// Set BW to 25 kHz
3508	tx_p1_bw = 3;
3509	tx_p2_bw2 = 7;
3510	}
3511	else if (bw > 37500 and bw <= 75000){
3512	// Set BW to 50 kHz
3513	tx_p1_bw = 3;
3514	tx_p2_bw2 = 3;
3515	}
3516	else if (bw > 75000 and bw <= 150000){
3517	// Set BW to 100 kHz
3518	tx_p1_bw = 3;
3519	tx_p2_bw2 = 1;
3520	}
3521	else if (bw > 150000 and bw <= 425000){
3522	// Set BW to 200 kHz
3523	tx_p1_bw = 3;
3524	tx_p2_bw2 = 0;
3525	}
3526	else if (bw > 425000 and bw <= 1125000){
3527	// Set BW to 750 kHz
3528	tx_p1_bw = 1;
3529	tx_p2_bw2 = 15;
3530	}
3531	else if (bw > 1125000 and bw <= 2250000){
3532	// Set BW to 1.5 MHz
3533	tx_p1_bw = 1;
3534	tx_p2_bw2 = 7;
3535	}
3536	else if (bw > 2250000 and bw <= 4500000){
3537	// Set BW to 3 MHz
3538	tx_p1_bw = 1;
3539	tx_p2_bw2 = 3;
3540	}
3541	else if (bw > 4500000 and bw <= 9000000){
3542	// Set BW to 6 MHz
3543	tx_p1_bw = 1;
3544	tx_p2_bw2 = 1;
3545	}
3546	else if (bw > 9000000 and bw <= 13000000){
3547	// Set BW to 12 MHz
3548	tx_p1_bw = 1;
3549	tx_p2_bw2 = 0;
3550	}
3551	else if (bw > 13000000){
3552	// Set BW to 14+ MHz
3553	tx_p1_bw = 0;
3554	tx_p2_bw2 = 0;
3555	}
3556	set_reg_173();
3557	set_reg_174();
3558	return true; //always returning true..may have to change this
3559	}
3560
3561	void rfic :: set_fb_bw(float bw){
3562	//
3563	//@param bw{ desired bandwidth in Hz
3564	//
3565	// Available bandwidth{ 5 MHz to 14+ MHz (baseband)
3566	// FIXME
3567	std::cout<<"Desired bandwidth :"<< bw<<std::endl;
3568	if (bw <= 7500000){
3569	// Set BW to 5 MHz
3570	tx_bb_fdbk_bw = 3;
3571	}
3572	else if (bw > 7500000 and bw <= 12000000){
3573	// Set BW to 10 MHz
3574	tx_bb_fdbk_bw = 1;
3575	}
3576	else if (bw > 12000000){
3577	// Set BW to 14+ MHz
3578	tx_bb_fdbk_bw = 0;
3579	}
3580	set_reg_156();
3581	}
3582
3583	void rfic :: enable_tx_fb(){
3584	//
3585	// Enable transmitter feedback to RX port for DC offset correction, etc.
3586	//
3587	// FIXME
3588	std::cout<<"Enabling Transmit Feedback"<<std::endl;
3589
3590	// Disable RX Filter
3591	rx_foe = 0;
3592	set_reg_196();
3593
3594	// Enable Baseband Feedback, TX I and Q via RX I and Q
3595	tx_bb_fdbk_en = 3;
3596	set_reg_157();
3597
3598	// Disable Baseband Feedback Calibration
3599	// FIXME
3600	//tx_bb_fdbk_cal_en = 0
3601
3602	// Enable Baseband Feedback Cartesian Forward Path
3603	tx_bb_fdbk_cart_fwd_en = 1;
3604	set_reg_156();
3605
3606	// Enable Cartesian Feedback Path
3607	tx_cart_en = 1;
3608	set_reg_160();
3609
3610	// Enable Cartesian Feedback
3611	CartesianFeedbackpathenable = 1;
3612
3613	// Enable Cartesian Feedback Path DCOC
3614	CartesianFeedbackpathDCOCenable = 1;
3615	set_reg_166();
3616
3617	// Set Cartesian Feedback Path Amplifier Gain
3618	CartesianFBpathAmp1Gain = 0;
3619	CartesianFBpathAmp2Gain = 0;
3620	CartesianFBpathAmp3Gain = 0;
3621	CartesianFBpathAmp4Gain = 0;
3622	set_reg_169();
3623
3624	// Enable Cartesian Feedback Path Zero
3625	CartesianFBpathZeroEnable = 1;
3626	set_reg_170();
3627	}
3628
3629	void rfic :: disable_tx_fb(){
3630	//
3631	// Disable transmitter feedback to RX port
3632	//
3633	// FIXME
3634	std::cout<<"Disabling Transmit Feedback"<<std::endl;
3635
3636	// Enable RX Filter
3637	rx_foe = 1;
3638	set_reg_196();
3639
3640	// Disable Baseband Feedback
3641	tx_bb_fdbk_en = 0;
3642	set_reg_157();
3643
3644	// Enable Baseband Feedback Calibration
3645	// FIXME
3646	//tx_bb_fdbk_cal_en = 1
3647
3648	// Disable Baseband Feedback Cartesian Forward Path
3649	tx_bb_fdbk_cart_fwd_en = 0;
3650	set_reg_156();
3651
3652	// Disable Cartesian Feedback Path
3653	tx_cart_en = 0;
3654	set_reg_160();
3655
3656	// Disable Cartesian Feedback
3657	CartesianFeedbackpathenable = 0;
3658
3659	// Disable Cartesian Feedback Path DCOC
3660	CartesianFeedbackpathDCOCenable = 0;
3661	set_reg_166();
3662
3663	// Set Cartesian Feedback Path Amplifier Gain
3664	CartesianFBpathAmp1Gain = 3;
3665	CartesianFBpathAmp2Gain = 3;
3666	CartesianFBpathAmp3Gain = 3;
3667	CartesianFBpathAmp4Gain = 3;
3668	set_reg_169();
3669
3670	// Disable Cartesian Feedback Path Zero
3671	CartesianFBpathZeroEnable = 0;
3672	set_reg_170();
3673	}
3674
3675
3676	int rfic :: RSSI_fade(){
3677	// Return fade, clip from the two RX-side ADCs.
3678	//@returns fade, clip
3679	// variables proportional to how much fading (low signal strength)
3680	// or clipping (high signal strength) is going on
3681
3682	// Turn off test mux
3683	int fade;
3684	TestMuxBufferEnable = 0; //Disable Test Mux Buffer
3685	TestMuxEnable = 0; //Disable Test Mux
3686	TestMuxSetting = 0; //Four Output Description (Test1, Test2, Test3, Test4)
3687	set_reg_222();
3688
3689	// Turn on on-channel detectors
3690	// Off-channel doesn't work - leave it off
3691	rx_onchen = 1; //Enables on-channel detector.
3692	rx_offchen = 0; //Disables off-channel detector
3693	set_reg_196();
3694
3695	// Set clip and fade thresholds
3696	rx_offch = 1; //Sets the Clip Threshold for the Off-channel Detector
3697	rx_onchf = 0; //Sets the Fade Threshold for the On-channel Detector relative to the On-channel clip point.
3698	rx_onchc = 2; //Sets the Clip Threshold for the On-channel Detector
3699	set_reg_197();
3700
3701	fade = usrp()->read_aux_adc(d_which, 0);
3702	return fade;
3703	}
3704	int rfic :: RSSI_clip(){
3705	// Return fade, clip from the two RX-side ADCs.
3706	//@returns fade, clip
3707	// variables proportional to how much fading (low signal strength)
3708	// or clipping (high signal strength) is going on
3709
3710	// Turn off test mux
3711	int clip;
3712	TestMuxBufferEnable = 0; //Disable Test Mux Buffer
3713	TestMuxEnable = 0; //Disable Test Mux
3714	TestMuxSetting = 0; //Four Output Description (Test1, Test2, Test3, Test4)
3715	set_reg_222();
3716
3717	// Turn on on-channel detectors
3718	// Off-channel doesn't work - leave it off
3719	rx_onchen = 1; //Enables on-channel detector.
3720	rx_offchen = 0; //Disables off-channel detector
3721	set_reg_196();
3722
3723	// Set clip and fade thresholds
3724	rx_offch = 1; //Sets the Clip Threshold for the Off-channel Detector
3725	rx_onchf = 0; //Sets the Fade Threshold for the On-channel Detector relative to the On-channel clip point.
3726	rx_onchc = 2; //Sets the Clip Threshold for the On-channel Detector
3727	set_reg_197();
3728
3729	clip = usrp()->read_aux_adc(d_which, 1);
3730	return clip;
3731	}
3732
3733
3734	/*****************************************************************************/
3735
3736
3737	struct rfic_table_entry {
3738	rfic_key key;
3739	boost::weak_ptr<rfic> value;
3740
3741	rfic_table_entry(const rfic_key &_key, boost::weak_ptr<rfic> _value)
3742	: key(_key), value(_value) {}
3743	};
3744
3745	typedef std::vector<rfic_table_entry> rfic_table;
3746
3747	static boost::mutex s_table_mutex;
3748	static rfic_table s_table;
3749
3750	static rfic_sptr
3751	_get_or_make_rfic(usrp_basic_sptr usrp, int which)
3752	{
3753	rfic_key key = {usrp->serial_number(), which};
3754
3755	boost::mutex::scoped_lock guard(s_table_mutex);
3756
3757	for (rfic_table::iterator p = s_table.begin(); p != s_table.end();){
3758	if (p->value.expired()) // weak pointer is now dead
3759	p = s_table.erase(p); // erase it
3760	else {
3761	if (key == p->key){ // found it
3762	return rfic_sptr(p->value);
3763	}
3764	else
3765	++p; // keep looking
3766	}
3767	}
3768
3769	// We don't have the rfic we're looking for
3770
3771	// create a new one and stick it in the table.
3772	rfic_sptr r(new rfic(usrp, which));
3773	rfic_table_entry t(key, r);
3774	s_table.push_back(t);
3775
3776	return r;
3777	}
3778
3779
3780	/*****************************************************************************/
3781
3782
3783
3784	db_rfic_base::db_rfic_base(usrp_basic_sptr usrp, int which)
3785	: db_base(usrp, which)
3786	{
3787	/*
3788	* Abstract base class for all rfic boards.
3789	*
3790	* Derive board specific subclasses from db_rfic_base_{tx,rx}
3791	*
3792	* @param usrp: instance of usrp.source_c
3793	* @param which: which side: 0 or 1 corresponding to side A or B respectively
3794	* @type which: int
3795	*/
3796
3797	d_rfic = _get_or_make_rfic(usrp, which);
3798	}
3799
3800	db_rfic_base::~db_rfic_base()
3801	{
3802	}
3803
3804
3805	bool
3806	db_rfic_base::is_quadrature()
3807	{
3808	/*
3809	* Return True if this board requires both I & Q analog channels.
3810	*
3811	* This bit of info is useful when setting up the USRP Rx mux register.
3812	*/
3813	return true;
3814	}
3815
3816
3817	double
3818	db_rfic_base::freq_min()
3819	{
3820	return 2.5e6;
3821	}
3822
3823
3824	double
3825	db_rfic_base::freq_max()
3826	{
3827	return 1e8;
3828	}
3829
3830
3831	void
3832	db_rfic_base::shutdown_common()
3833	{
3834	// If the usrp_basic in the rfic is the same as the usrp_basic
3835	// in the daughterboard, shutdown the rfic now (when only one of Tx
3836	// and Rx is open, this is always true).
3837
3838	if (d_rfic->usrp() == usrp()){
3839	//std::cerr << "db_rfic_base::shutdown_common: same -> shutting down\n";
3840	d_rfic->shutdown();
3841	}
3842	else {
3843	//std::cerr << "db_rfic_base::shutdown_common: different -> ignoring\n";
3844	}
3845	}
3846
3847	/******************************************************************************************************/
3848
3849	////////////
3850	db_rfic_tx::db_rfic_tx(usrp_basic_sptr usrp, int which)
3851	: db_rfic_base(usrp, which)
3852	{
3853
3854	//select_tx_antenna(abc);
3855	d_rfic->set_reg_0();
3856	d_rfic->set_reg_1();
3857	d_rfic->set_reg_2();
3858	d_rfic->set_reg_3();
3859	d_rfic->set_reg_4();
3860	d_rfic->set_reg_5();
3861	d_rfic->set_reg_6();
3862	d_rfic->set_reg_7();
3863	d_rfic->set_reg_8();
3864	d_rfic->set_reg_9();
3865	d_rfic->set_reg_10();
3866	d_rfic->set_reg_12();
3867	d_rfic->set_reg_13();
3868	d_rfic->set_reg_14();
3869	d_rfic->set_reg_15();
3870	d_rfic->set_reg_16();
3871	d_rfic->set_reg_17();
3872	d_rfic->set_reg_18();
3873	d_rfic->set_reg_19();
3874	d_rfic->set_reg_20();
3875	d_rfic->set_reg_21();
3876	d_rfic->set_reg_22();
3877	d_rfic->set_reg_23();
3878	d_rfic->set_reg_24();
3879	d_rfic->set_reg_29();
3880	d_rfic->set_reg_30();
3881	d_rfic->set_reg_31();
3882	d_rfic->set_reg_32();
3883	d_rfic->set_reg_33();
3884	d_rfic->set_reg_34();
3885	d_rfic->set_reg_35();
3886	d_rfic->set_reg_36();
3887	d_rfic->set_reg_37();
3888	d_rfic->set_reg_38();
3889	d_rfic->set_reg_39();
3890	d_rfic->set_reg_40();
3891	d_rfic->set_reg_41();
3892	d_rfic->set_reg_42();
3893	d_rfic->set_reg_43();
3894	d_rfic->set_reg_156();
3895	d_rfic->set_reg_157();
3896	d_rfic->set_reg_158();
3897	d_rfic->set_reg_159();
3898	d_rfic->set_reg_160();
3899	d_rfic->set_reg_161();
3900	d_rfic->set_reg_162();
3901	d_rfic->set_reg_163();
3902	d_rfic->set_reg_164();
3903	d_rfic->set_reg_165();
3904	d_rfic->set_reg_166();
3905	d_rfic->set_reg_167();
3906	d_rfic->set_reg_168();
3907	d_rfic->set_reg_169();
3908	d_rfic->set_reg_170();
3909	d_rfic->set_reg_171();
3910	d_rfic->set_reg_172();
3911	d_rfic->set_reg_173();
3912	d_rfic->set_reg_174();
3913	d_rfic->set_reg_175();
3914	d_rfic->set_reg_176();
3915	d_rfic->set_reg_177();
3916	d_rfic->set_reg_178();
3917	d_rfic->set_reg_179();
3918	d_rfic->set_reg_180();
3919	d_rfic->set_reg_181();
3920
3921	// Get digital block out of digital reset state
3922	d_rfic->Rst_n_async = 1;
3923	d_rfic->set_reg_24();
3924
3925	// Turn on forward baseband reference section
3926	d_rfic->tx_bb_en = 1;
3927	// FIXME
3928	//d_rfic->set_reg_156();
3929
3930	// Unroutes the Cartesian error signal through the BB Correction feedback
3931	// FIXME
3932	d_rfic->tx_bb_fdbk_cart_err_en = 0;
3933
3934	// Routes the Cartesian feedback signal through the BB Correction feedback
3935	// FIXME
3936	d_rfic->tx_bb_fdbk_cart_fb_en = 1;
3937	d_rfic->set_reg_156();
3938
3939	// Turn on baseband feedback section
3940	// FIXME
3941	//d_rfic->tx_bb_fdbk_en = 3;
3942	//d_rfic->set_reg_157();
3943
3944	// Turn on forward RF transmit path
3945	d_rfic->RFForwardPathEnable_toMUX = 1;
3946	d_rfic->set_reg_175();
3947
3948	// Turn on Cartesian FB path switch to forward summer
3949	d_rfic->CartesianFBpathSwitchtoforwardSummer = 1;
3950	d_rfic->set_reg_168();
3951
3952	// Turn on Cartesian zero
3953	d_rfic->CartesianFBpathZeroEnable = 1;
3954	d_rfic->set_reg_170();
3955
3956	// Select TX output path, default tx1
3957	// FIXME
3958	d_rfic->tx_output_channel_sel = 2;
3959	//d_rfic->tx_output_channel_sel = 1;
3960	d_rfic->set_reg_172();
3961
3962	// Set TX Channel 1 Gain
3963	// The gain control on TX channel 1 is controlled by this DAC
3964	// The maximum voltage is 2.2 volts, which corresponds to 2750
3965	// This controls about 35 dB of gain ONLY ON TX 1
3966	d_rfic->usrp()->write_aux_dac(d_rfic->d_which, 3, 2750);
3967
3968
3969	// POR On. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
3970	d_rfic->Clk_driver_en = 1;
3971
3972	// POR On
3973	d_rfic->qu_reg_en = 1;
3974
3975	// POR On
3976	d_rfic->qq_reg_en = 1;
3977
3978	// POR Off
3979	d_rfic->win_rst = 0;
3980
3981	// POR On
3982	d_rfic->fineEn = 0;
3983
3984	// POR Off
3985	d_rfic->fineEnb = 1;
3986
3987	// POR On
3988	//d_rfic->rsffEn = 0;
3989
3990	// POR On
3991	d_rfic->dl_en = 1;
3992
3993	// POR On
3994	d_rfic->cp_en = 1;
3995
3996	d_rfic->set_reg_20();
3997	d_rfic->set_reg_21();
3998	}
3999
4000	db_rfic_tx::~db_rfic_tx()
4001	{
4002	// print "rfic_base_tx.__del__"
4003	// Power down
4004
4005	// Turn off output channel
4006	d_rfic->tx_output_channel_sel = 0;
4007	d_rfic->set_reg_172();
4008
4009	// Turn off forward RF transmit path
4010	d_rfic->RFForwardPathEnable_toMUX = 0;
4011	d_rfic->set_reg_17();
4012
4013	// Turn off forward baseband reference section
4014	d_rfic->tx_bb_en = 0;
4015	d_rfic->set_reg_156();
4016
4017	// Unroutes the Cartesian error signal through the BB Correction feedback
4018	// FIXME
4019	d_rfic->tx_bb_fdbk_cart_err_en = 0;
4020
4021	// Unroutes the Cartesian feedback signal through the BB Correction feedback
4022	d_rfic->tx_bb_fdbk_cart_fb_en = 0;
4023	d_rfic->set_reg_156();
4024
4025	// Turn off Cartesian FB path switch to forward summer
4026	d_rfic->CartesianFBpathSwitchtoforwardSummer = 0;
4027	d_rfic->set_reg_168();
4028
4029	// Turn off Cartesian zero
4030	d_rfic->CartesianFBpathZeroEnable = 0;
4031	d_rfic->set_reg_170();
4032
4033	// Turn off baseband feedback section
4034	// FIXME
4035	//d_rfic->tx_bb_fdbk_en = 0;
4036	//d_rfic->set_reg_157()
4037
4038	// POR Off. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
4039	d_rfic->Clk_driver_en = 0;
4040
4041	// POR Off
4042	d_rfic->qu_reg_en = 0;
4043
4044	// POR Off
4045	d_rfic->qq_reg_en = 0;
4046
4047	// POR Off
4048	d_rfic->win_rst = 0;
4049
4050	// POR Off
4051	d_rfic->fineEn = 0;
4052
4053	// POR Off
4054	d_rfic->fineEnb = 0;
4055
4056	// POR Off
4057	//d_rfic->rsffEn = 0;
4058
4059	// POR Off
4060	d_rfic->dl_en = 0;
4061
4062	// POR Off
4063	d_rfic->cp_en = 0;
4064
4065	d_rfic->set_reg_20();
4066	d_rfic->set_reg_21();
4067
4068	// Put digital block in digital reset state
4069	d_rfic->Rst_n_async = 0;
4070	d_rfic->set_reg_24();
4071	shutdown();
4072
4073
4074	}
4075
4076	bool
4077	db_rfic_tx::select_tx_antenna(std::string which_antenna){
4078	//
4079	//Specify which antenna port to use for transmission.
4080	//@param which_antenna: either 'tx1', 'tx2' or 'tx3'
4081	//
4082	if (which_antenna == "tx1"){
4083	d_rfic->tx_output_channel_sel = 1;
4084	d_rfic->set_reg_172();
4085	}
4086	else if (which_antenna == "tx2"){
4087	d_rfic->tx_output_channel_sel = 2;
4088	d_rfic->set_reg_172();
4089	}
4090	else if (which_antenna == "tx3"){
4091	d_rfic->tx_output_channel_sel = 4;
4092	d_rfic->set_reg_172();
4093	}
4094	else{
4095	std::cout<< "which_antenna must be either tx1/0 , tx2/1 or tx3/2"<<std::endl;
4096	return false;
4097	}
4098
4099	return true;
4100	}
4101
4102
4103	bool
4104	db_rfic_tx::select_tx_antenna(int which_antenna){
4105	//
4106	//Specify which antenna port to use for transmission.
4107	//@param which_antenna: either 'tx1', 'tx2' or 'tx3'
4108	//
4109	if (which_antenna == 0){
4110	d_rfic->tx_output_channel_sel = 1;
4111	d_rfic->set_reg_172();
4112	}
4113	else if (which_antenna == 1){
4114	d_rfic->tx_output_channel_sel = 2;
4115	d_rfic->set_reg_172();
4116	}
4117	else if (which_antenna == 2){
4118	d_rfic->tx_output_channel_sel = 4;
4119	d_rfic->set_reg_172();
4120	}
4121	else{
4122	std::cout<< "which_antenna must be either tx1/0 , tx2/1 or tx3/2"<<std::endl;
4123	return false;
4124	}
4125
4126	return true;
4127	}
4128
4129	void
4130	db_rfic_tx::shutdown()
4131	{
4132	if (!d_is_shutdown){
4133	d_is_shutdown = true;
4134	shutdown_common();
4135	}
4136	}
4137
4138	float
4139	db_rfic_tx::gain_min()
4140	{
4141	return 0.0;
4142	}
4143
4144	float
4145	db_rfic_tx::gain_max()
4146	{
4147	return 45.0;
4148	}
4149
4150	bool
4151	db_rfic_tx::set_gain(float gain)
4152	{
4153	return d_rfic->set_tx_gain(gain);
4154	}
4155
4156	struct freq_result_t
4157	db_rfic_tx::set_freq(double target_frequency)
4158	{
4159	return d_rfic->set_tx_freq(target_frequency);
4160	}
4161
4162	bool
4163	db_rfic_tx::set_phase(int phase)
4164	{
4165	return d_rfic->set_tx_phase(phase);
4166	}
4167
4168	bool
4169	db_rfic_tx::set_bw(float bw)
4170	{
4171	return d_rfic->set_tx_bw(bw);
4172	}
4173
4174	bool
4175	db_rfic_tx::spectrum_inverted()
4176	{
4177	return true;
4178	}
4179
4180	float
4181	db_rfic_tx::gain_db_per_step()
4182	{
4183	return d_rfic->usrp()->pga_db_per_step();
4184	}
4185
4186
4187	db_rfic_rx::db_rfic_rx(usrp_basic_sptr usrp, int which)
4188	: db_rfic_base(usrp, which)
4189	{
4190	std::string abc = "MIX5";
4191	this->select_rx_antenna(abc);
4192	d_rfic->set_reg_48();
4193	d_rfic->set_reg_49();
4194	d_rfic->set_reg_50();
4195	d_rfic->set_reg_51();
4196	d_rfic->set_reg_52();
4197	d_rfic->set_reg_53();
4198	d_rfic->set_reg_54();
4199	d_rfic->set_reg_55();
4200	d_rfic->set_reg_56();
4201	d_rfic->set_reg_57();
4202	d_rfic->set_reg_58();
4203	d_rfic->set_reg_60();
4204	d_rfic->set_reg_61();
4205	d_rfic->set_reg_62();
4206	d_rfic->set_reg_63();
4207	d_rfic->set_reg_64();
4208	d_rfic->set_reg_65();
4209	d_rfic->set_reg_66();
4210	d_rfic->set_reg_67();
4211	d_rfic->set_reg_68();
4212	d_rfic->set_reg_69();
4213	d_rfic->set_reg_70();
4214	d_rfic->set_reg_71();
4215	d_rfic->set_reg_72();
4216	d_rfic->set_reg_77();
4217	d_rfic->set_reg_78();
4218	d_rfic->set_reg_79();
4219	d_rfic->set_reg_80();
4220	d_rfic->set_reg_81();
4221	d_rfic->set_reg_82();
4222	d_rfic->set_reg_83();
4223	d_rfic->set_reg_84();
4224	d_rfic->set_reg_85();
4225	d_rfic->set_reg_86();
4226	d_rfic->set_reg_87();
4227	d_rfic->set_reg_88();
4228	d_rfic->set_reg_89();
4229	d_rfic->set_reg_90();
4230	d_rfic->set_reg_91();
4231	d_rfic->set_reg_96();
4232	d_rfic->set_reg_97();
4233	d_rfic->set_reg_98();
4234	d_rfic->set_reg_99();
4235	d_rfic->set_reg_104();
4236	d_rfic->set_reg_105();
4237	d_rfic->set_reg_106();
4238	d_rfic->set_reg_107();
4239	d_rfic->set_reg_108();
4240	d_rfic->set_reg_109();
4241	d_rfic->set_reg_110();
4242	d_rfic->set_reg_111();
4243	d_rfic->set_reg_112();
4244	d_rfic->set_reg_113();
4245	d_rfic->set_reg_114();
4246	d_rfic->set_reg_116();
4247	d_rfic->set_reg_117();
4248	d_rfic->set_reg_118();
4249	d_rfic->set_reg_119();
4250	d_rfic->set_reg_120();
4251	d_rfic->set_reg_121();
4252	d_rfic->set_reg_122();
4253	d_rfic->set_reg_123();
4254	d_rfic->set_reg_124();
4255	d_rfic->set_reg_125();
4256	d_rfic->set_reg_126();
4257	d_rfic->set_reg_127();
4258	d_rfic->set_reg_128();
4259	d_rfic->set_reg_133();
4260	d_rfic->set_reg_134();
4261	d_rfic->set_reg_135();
4262	d_rfic->set_reg_136();
4263	d_rfic->set_reg_137();
4264	d_rfic->set_reg_138();
4265	d_rfic->set_reg_139();
4266	d_rfic->set_reg_140();
4267	d_rfic->set_reg_141();
4268	d_rfic->set_reg_142();
4269	d_rfic->set_reg_143();
4270	d_rfic->set_reg_144();
4271	d_rfic->set_reg_145();
4272	d_rfic->set_reg_146();
4273	d_rfic->set_reg_147();
4274	d_rfic->set_reg_152();
4275	d_rfic->set_reg_153();
4276	d_rfic->set_reg_192();
4277	d_rfic->set_reg_193();
4278	d_rfic->set_reg_194();
4279	d_rfic->set_reg_195();
4280	d_rfic->set_reg_196();
4281	d_rfic->set_reg_197();
4282	d_rfic->set_reg_198();
4283	d_rfic->set_reg_199();
4284	d_rfic->set_reg_200();
4285	d_rfic->set_reg_201();
4286	d_rfic->set_reg_202();
4287	d_rfic->set_reg_203();
4288	d_rfic->set_reg_204();
4289	d_rfic->set_reg_205();
4290	d_rfic->set_reg_206();
4291	d_rfic->set_reg_207();
4292
4293	// Get digital block out of digital reset state
4294	d_rfic->Rst_n_async_3 = 1;
4295	d_rfic->set_reg_128();
4296
4297	// Set RX LNA port to LNA1 (SGO non-chopping mixer)
4298	// FIXME
4299	//d_rfic->rx_lna = 1;
4300	d_rfic->rx_lna = 5;
4301
4302	// Set LNA bias
4303	d_rfic->rx_lnab = 1;
4304
4305	// Enable LO clock to mixer
4306	d_rfic->rx_rxchen = 1;
4307
4308	d_rfic->set_reg_205();
4309
4310	// Enable RX Filter
4311	d_rfic->rx_fen = 1;
4312
4313	// Enable baseband filter chopper clock
4314	d_rfic->rx_chcken = 1;
4315
4316	// Enable chopper clock to all mixers
4317	d_rfic->rx_cen = 7;
4318
4319	// Set chopper divide setting
4320	// FIXME
4321	//d_rfic->rx_chck = 0
4322	d_rfic->rx_chck = 1;
4323
4324	d_rfic->set_reg_195();
4325
4326	// Enable filter output
4327	d_rfic->rx_foe = 1;
4328
4329	// Enable on-channel detector
4330	//d_rfic->rx_onchen = 1
4331
4332	// Enable off-channel detector
4333	//d_rfic->rx_offchen = 1
4334
4335
4336	d_rfic->set_reg_196();
4337
4338	// Set BQ filter Q to 1.33
4339	d_rfic->rx_qs = 2;
4340
4341	// Set BQ resistor value to 1.4 kohms
4342	d_rfic->rx_rq = 0;
4343
4344	d_rfic->set_reg_198();
4345
4346	// Set VGA resistor value to 2.5 kohms
4347	d_rfic->rx_rv = 0;
4348
4349	// Set PMA Rf resistor to 5 kohms
4350	d_rfic->rx_rfp = 00;
4351
4352	d_rfic->set_reg_199();
4353
4354	// Set compensation control
4355	d_rfic->rx_cc_2to0 = 0;
4356
4357	d_rfic->set_reg_203();
4358
4359	// Enable DCOC DAC
4360	d_rfic->rx_den = 1;
4361
4362	d_rfic->set_reg_192();
4363
4364	// Enable DCOC comparator
4365	d_rfic->rx_cmpen = 1;
4366
4367	d_rfic->set_reg_193();
4368
4369	// RC Tune enable
4370	// FIXME
4371	//d_rfic->rx_ten = 1;
4372	d_rfic->rx_ten = 0;
4373
4374	// RC Tune ramp circuit enable
4375	// FIXME
4376	//d_rfic->rx_ren = 1;
4377	d_rfic->rx_ren = 0;
4378
4379	// Select DCOC/RC Tune divider, divide by 8
4380	d_rfic->rx_dv = 3;
4381
4382	d_rfic->set_reg_194();
4383
4384	// Enable DCOC
4385	d_rfic->rx_dcoc = 1;
4386
4387	d_rfic->set_reg_193();
4388
4389	// POR On. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
4390	d_rfic->Clk_driver_en_3 = 1;
4391
4392	// POR On
4393	d_rfic->qu_reg_en_3 = 1;
4394
4395	// POR On
4396	d_rfic->qq_reg_en_3 = 1;
4397	// POR Off
4398	d_rfic->win_rst_3 = 0;
4399
4400	// POR On
4401	d_rfic->fineEn_3 = 0 ;
4402
4403	// POR Off
4404	d_rfic->fineEnb_3 = 1;
4405
4406	// POR Off
4407	//d_rfic->rsffEn_3 = 0;
4408
4409	// POR On
4410	d_rfic->dl_en_3 = 1;
4411
4412	// POR On
4413	d_rfic->cp_en_3 = 1;
4414
4415	d_rfic->set_reg_124();
4416	d_rfic->set_reg_125();
4417	}
4418
4419	db_rfic_rx::~db_rfic_rx()
4420	{
4421	// std::cout << "inside db_rfic_rx destructor "<< std::endl;
4422	// Power down
4423
4424	// Set RX LNA path (off)
4425	d_rfic->rx_lna = 0;
4426
4427	// Disable LO clock to mixer
4428	d_rfic->rx_rxchen = 0;
4429
4430	d_rfic->set_reg_205();
4431	// Disable RX Filter
4432	d_rfic->rx_fen = 0;
4433
4434	// Disable baseband filter chipper clock
4435	d_rfic->rx_chcken = 0;
4436
4437	// Disable chopper clock to all mixers
4438	d_rfic->rx_cen = 0;
4439	d_rfic->set_reg_195();
4440
4441	// Disable filter output
4442	d_rfic->rx_foe = 0;
4443
4444	// Disable on-channel detector
4445	d_rfic->rx_onchen = 0;
4446
4447	// Disable off-channel detector
4448	d_rfic->rx_offchen = 0;
4449
4450	d_rfic->set_reg_196();
4451
4452	// Disable DCOC DAC
4453	d_rfic->rx_den = 0;
4454
4455	d_rfic->set_reg_192();
4456
4457	// Disable DCOC comparator
4458	d_rfic->rx_cmpen = 0;
4459
4460	d_rfic->set_reg_193();
4461
4462	// RC Tune disable
4463	d_rfic->rx_ten = 0;
4464
4465	// RC Tune ramp circuit disable
4466	d_rfic->rx_ren = 0;
4467
4468	d_rfic->set_reg_194();
4469
4470	// Disable DCOC
4471	d_rfic->rx_dcoc = 0;
4472
4473	d_rfic->set_reg_193();
4474
4475	// POR Off. This enables the clock that drives the digital block (which provides the tap selection process). It must be enabled to generate an output. See Byp_fine, address 10, bit 6
4476	d_rfic->Clk_driver_en_3 = 0;
4477
4478	// POR Off
4479	d_rfic->qu_reg_en_3 = 0;
4480
4481	// POR Off
4482	d_rfic->qq_reg_en_3 = 0;
4483
4484	// POR Off
4485	d_rfic->win_rst_3 = 0;
4486
4487	// POR Off
4488	d_rfic->fineEn_3 = 0;
4489
4490	// POR Off
4491	d_rfic->fineEnb_3 = 0;
4492
4493	// POR Off
4494	//d_rfic->rsffEn_3 = 0;
4495
4496	// POR Off
4497	d_rfic->dl_en_3 = 0;
4498
4499	// POR Off
4500	d_rfic->cp_en_3 = 0;
4501
4502	d_rfic->set_reg_124();
4503	d_rfic->set_reg_125();
4504
4505	// Put digital block into digital reset state
4506	d_rfic->Rst_n_async_3 = 0;
4507	d_rfic->set_reg_58();
4508	shutdown();
4509
4510
4511	}
4512
4513	void
4514	db_rfic_rx::shutdown()
4515	{
4516	if (!d_is_shutdown){
4517	d_is_shutdown = true;
4518	shutdown_common();
4519	}
4520	}
4521
4522	bool
4523	db_rfic_rx::select_rx_antenna(std::string which_antenna){
4524	//
4525	//Specif(y which antenna port to use for transmission.
4526	//@param which_antenna: either LNA1/0, LNA2/1, LNA3/2, LNA4/3 or MIX5/4
4527	//
4528	//std::cout<<"inside select rx antenna..antenna used is :"<<which_antenna
4529	which_antenna = "MIX5";
4530	if( which_antenna == "LNA1"){
4531	d_rfic->rx_lna = 1;
4532	d_rfic->set_reg_205();
4533	}
4534	else if( which_antenna == "LNA2"){
4535	d_rfic->rx_lna = 2;
4536	d_rfic->set_reg_205();
4537	}
4538	else if( which_antenna == "LNA3"){
4539	d_rfic->rx_lna = 3;
4540	d_rfic->set_reg_205();
4541	}
4542	else if( which_antenna == "LNA4"){
4543	d_rfic->rx_lna = 4;
4544	d_rfic->set_reg_205();
4545	}
4546	else if( which_antenna == "MIX5"){
4547	d_rfic->rx_lna = 5;
4548	d_rfic->set_reg_205();
4549	}
4550	else{
4551	std::cout<< "FJAHFJDH which_antenna must be either LNA1/0, LNA2/1, LNA3/2, LNA4/3 or MIX5/4"<<std::endl;
4552	return false;
4553	}
4554
4555	return true;
4556	}
4557
4558	bool
4559	db_rfic_rx::select_rx_antenna(int which_antenna){
4560	//
4561	//Specif(y which antenna port to use for transmission.
4562	//@param which_antenna: either 'rx1', 'rx2' or 'rx3'
4563	//
4564	if( which_antenna == 0){
4565	d_rfic->rx_lna = 1;
4566	d_rfic->set_reg_205();
4567	}
4568	else if( which_antenna == 1){
4569	d_rfic->rx_lna = 2;
4570	d_rfic->set_reg_205();
4571	}
4572	else if( which_antenna == 2){
4573	d_rfic->rx_lna = 3;
4574	d_rfic->set_reg_205();
4575	}
4576	else if( which_antenna == 3){
4577	d_rfic->rx_lna = 4;
4578	d_rfic->set_reg_205();
4579	}
4580	else if( which_antenna == 4){
4581	d_rfic->rx_lna = 5;
4582	d_rfic->set_reg_205();
4583	}
4584	else{
4585	std::cout<< "which_antenna must be either LNA1/0, LNA2/1, LNA3/2, LNA4/3 or MIX5/4"<<std::endl;
4586	return false;
4587	}
4588	return true;
4589	}
4590
4591	float
4592	db_rfic_rx::gain_min()
4593	{
4594	return 0.0;
4595	}
4596
4597	float
4598	db_rfic_rx::gain_max()
4599	{
4600	return 40.0;
4601	}
4602
4603
4604	bool
4605	db_rfic_rx::set_gain(float gain)
4606	{
4607	return d_rfic->set_rx_gain(gain);
4608	}
4609
4610	struct freq_result_t
4611	db_rfic_rx::set_freq(double target_frequency)
4612	{
4613	return d_rfic->set_rx_freq(target_frequency);
4614	}
4615
4616	bool
4617	db_rfic_rx::set_phase(int phase)
4618	{
4619	return d_rfic->set_rx_phase(phase);
4620	}
4621
4622	bool
4623	db_rfic_rx::set_bw(float bw)
4624	{
4625	return d_rfic->set_rx_bw(bw);
4626	}
4627
4628	void
4629	db_rfic_rx::enable_fb(){
4630	// Enable transmitter feedback to receiver for DC offset, etc.
4631	d_rfic->enable_tx_fb();
4632	}
4633
4634	void
4635	db_rfic_rx::disable_tx_fb(){
4636	// Disable transmitter feedback to receiver
4637	return d_rfic->disable_tx_fb();
4638	}
4639	float
4640	db_rfic_rx::fb_gain_min(){
4641	return 0.0;
4642	}
4643
4644	float
4645	db_rfic_rx::fb_gain_max(){
4646	return 40.0;
4647	}
4648
4649	void
4650	db_rfic_rx::set_fb_gain(float gain){
4651	// Set feedback gain, in dB
4652	d_rfic->set_fb_gain(gain);
4653	}
4654
4655	bool
4656	db_rfic_rx::set_fb_freq(double target_freq){
4657	// Set feedback frequency, in Hz
4658	return d_rfic->set_fb_freq(target_freq);
4659	}
4660
4661	bool
4662	db_rfic_rx::set_fb_phase(int phase){
4663	// Set feedback phase offset, in degrees
4664	return d_rfic->set_fb_phase(phase);
4665	}
4666
4667	void
4668	db_rfic_rx::set_fb_bw(float bw){
4669	// Set feedback bandwidth, in Hz
4670	d_rfic->set_fb_bw(bw);
4671	}
4672
4673	int
4674	db_rfic_rx::RSSI_fade(){
4675	// Get received signal strength indicators
4676	// Returns fade
4677	// Fade is proportional to how often the signal is low
4678	return d_rfic->RSSI_fade();
4679	}
4680
4681	int
4682	db_rfic_rx::RSSI_clip(){
4683	// Get received signal strength indicators
4684	// Returns clip
4685	// Clip is proportional to how often the signal is high
4686	return d_rfic->RSSI_clip();
4687	}
4688
4689	float
4690	db_rfic_rx::gain_db_per_step()
4691	{
4692	return d_rfic->usrp()->pga_db_per_step();
4693	}
4694
4695	#endif
4696
4697

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