Changeset 500

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Timestamp:
10/04/09 12:36:56 (15 years ago)
Author:
sriram
Message:

Cleaning up debug statements and removing pointer return type from calc_freq_vars and calc_phase_vars(Updating values by reference in these functions nowX)

Files:
1 modified

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  • vtcross/branches/sriram/rfic/db_rfic.cc

    r483 r500  
    328328        bool set_tx_gain(float); 
    329329        void set_fb_gain(float); 
    330         int* calc_freq_vars(double,double); 
    331         int* calc_phase_vars(double,double,double); 
     330        void calc_freq_vars(double,double,int []); 
     331        void calc_phase_vars(double,double,double,int[]); 
    332332        struct freq_result_t set_rx_freq(double); 
    333333        struct freq_result_t set_tx_freq(double); 
     
    870870rfic::send_reg(int reg_no,int dat ) 
    871871{ 
    872     std::cout<<"value to be written on reg no "<<reg_no<<"is "<<dat<<std::endl; 
     872     
    873873    // dat is the data to write to register 0 
    874874    //spi_enable is the spi enables 
     
    878878    //Write 8 bit register 
    879879    //Set header 
    880     int hdr = int((reg_no << 1) & 0x7fff); 
    881     std::string abc = "105"; 
    882     //Set byte of write data 
    883     //char c = (char)((dat & 0xff)); 
    884     //char * d = &c; 
    885  
     880 
     881    std::cout<<"db_rfic.cc: Register no: "<<reg_no<<" ,Value: "<<dat<<std::endl; 
     882    //std::cout<<"db_rfic.cc:Value on the register before writing"<<get_reg(reg_no)<<std::endl; 
     883     
     884    int hdr = int((reg_no << 1) & 0x7fff); //since the 14 bit address lies from bits 1-14..0th bit is for auto increment..15th bit is for read/write 
     885    char c[1]; 
     886    c[0] = (char)(dat&0xff); 
     887    std::string s(c, 1); //s is the data to be sent to the register 
     888     
    886889    bool check; 
    887     std::cout<<"\nValue on the register before writing\n"<<get_reg(reg_no)<<std::endl; 
    888     check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, abc); 
    889     if (check) 
    890         std::cout<<"success"<<std::endl; 
    891     else 
    892         std::cout<<"fail"<<std::endl; 
    893     std::cout<<"\nValue on the register after ******** writing\n ***"<<get_reg(reg_no)<<"***"<<std::endl; 
    894890     
     891    check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, s); 
     892    //if (check) 
     893        //std::cout<<"db_rfic.cc: Write successful"<<std::endl; //Do not trust variable check! 
     894    //else 
     895        //std::cout<<"db_rfic.cc: Write failed"<<std::endl; 
     896    //std::cout<<"db_rfic.cc:Value on the register after ******** writing\n ***"<<get_reg(reg_no)<<"***"<<std::endl; 
     897    //if(reg_no == 60) 
     898        //get_reg(reg_no); 
    895899} 
    896900 
     
    899903{ 
    900904 
    901         std::cout<<"inside get reg and register to be read is "<<reg_num<<std::endl; 
    902         //Returns a vector containing the information in the first 320 registers in integer form 
     905    //Returns a vector containing the information in the first 320 registers in integer form 
    903906    //dat is the data to write to register 0 
    904907    //spi_enable is the spi enables 
     
    906909    //spi_format_no_header is the spi format, with no header 
    907910    //u is the instance of the USRP 
     911     
    908912    int hdr = 0; 
    909913    int dat = 0; 
    910     //Set byte of write data 
    911     //char c = (char)((dat & 0xff)); 
    912     //char * d = &c; 
    913     std::string d  = "0"; 
     914    char c[1]; 
     915    c[0] = (char)(dat&0xff); 
     916    std::string s(c, 1); //s is the data to be sent to the register 
     917     
    914918    bool check; 
    915     check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, d); 
     919    check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, s); 
    916920     
    917921    std::string r; //string to be read from the register 
    918     r = usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 
     922    r = usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); //Starts reading from register 0 since the previous write is on register 0 
    919923    r  = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 
    920924    r  = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 
    921925    r  = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 
    922926    r  = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 
    923     std::cout<<"the contents of all registers are\n***"<<r<<"*****"<<std::endl; 
     927    std::cout<<"db_rfic.cc: contents of all registers \n***"<<r<<"***"<<std::endl; 
    924928    char read_val = (char)r[reg_num]; 
    925929    return read_val; 
     
    23782382} 
    23792383 
    2380 int* rfic :: calc_freq_vars(double _Fclk,double _Fout){ 
     2384void rfic :: calc_freq_vars(double _Fclk,double _Fout,int ret_arr[]){ 
    23812385        // 
    23822386        //@param Fclk: Clock frequency of board (Hz) 
     
    23942398        float NpR; 
    23952399        int data1,data2,data3,temp,Ngt; 
    2396         int ret_arr[6]; 
     2400        //int ret_arr[6]; 
    23972401        if (_Fout > _Fclk / 4){ 
    23982402                NpR = pow(2,-26) * floor(pow(2,26) * _Fclk / _Fout); 
     
    24082412        } 
    24092413 
    2410         Ngt = data1;//need to speak to terry about this variable..is this a local variable or supposed to be a class attribute 
     2414        Ngt = data1; 
     2415 
    24112416        ret_arr[0]= Ngt; 
    24122417        NorNdiv4 = data2; 
    24132418        ret_arr[1]=NorNdiv4; 
     2419                         
    24142420        RorFrNpRdiv4_25to18 = data3 >> 18; 
    24152421        ret_arr[2]=RorFrNpRdiv4_25to18; 
     
    24222428        RorFrNpRdiv4_1to0 = data3 % int(pow(2,2)); 
    24232429        ret_arr[5]=RorFrNpRdiv4_1to0; 
    2424  
    2425         return ret_arr; 
    2426 } 
    2427  
    2428 int* rfic :: calc_phase_vars(double _Fclk, double _Fout,double phsh){ 
     2430                 
     2431} 
     2432 
     2433void rfic :: calc_phase_vars(double _Fclk, double _Fout,double phsh,int ret_arr[]){ 
    24292434        // 
    24302435        //@param _Fclk: Clock frequency of board (Hz) 
     
    24452450        float mod1,tmp,NpR,NpR_ph; 
    24462451        int data1,data2,data3,temp,Ngt_phsh,RorFrNpRdiv4_17to10_phsh,RorFrNpRdiv4_9to2_phsh,RorFrNpRdiv4_25to18_phsh,RorFrNpRdiv4_1to0_phsh; 
    2447         int ret_arr[6]; 
     2452         
    24482453        if (_Fout <= _Fclk / 4){ 
    24492454                mod1 = phsh - 360 * floor(phsh / 360); 
     
    24762481        Ngt_phsh = data1; 
    24772482        ret_arr[0]=Ngt_phsh; 
     2483 
    24782484        NorNdiv4_phsh = data2; 
    24792485        ret_arr[1]=NorNdiv4_phsh; 
     
    24892495        ret_arr[5]=RorFrNpRdiv4_1to0_phsh; 
    24902496 
    2491         return ret_arr; 
    24922497} 
    24932498 
     
    27442749 
    27452750        Foutrx = target_freq; 
    2746         int * ret_arr; 
    2747         ret_arr= calc_freq_vars(Fclk, try_freq); 
     2751        int  ret_arr[6]; 
     2752        calc_freq_vars(Fclk, try_freq,ret_arr); 
    27482753        Ngt3_3 = ret_arr[0]; 
    2749         NorNdiv4_3= ret_arr[1]; 
    2750         RorFrNpRdiv4_25to18_3= ret_arr[2]; 
    2751         RorFrNpRdiv4_17to10_3= ret_arr[3]; 
    2752         RorFrNpRdiv4_9to2_3= ret_arr[4]; 
    2753         RorFrNpRdiv4_1to0_3= ret_arr[5]; 
     2754        NorNdiv4_3= ret_arr[1]; 
     2755        RorFrNpRdiv4_25to18_3= ret_arr[2]; 
     2756        RorFrNpRdiv4_17to10_3= ret_arr[3]; 
     2757        RorFrNpRdiv4_9to2_3= ret_arr[4]; 
     2758        RorFrNpRdiv4_1to0_3= ret_arr[5]; 
     2759         
    27542760 
    27552761        set_reg_104(); 
     
    29712977        Fouttx = target_freq; 
    29722978 
    2973         int * ret_arr; 
    2974         ret_arr= calc_freq_vars(Fclk, try_freq); 
     2979        int  ret_arr[6]; 
     2980        calc_freq_vars(Fclk, try_freq,ret_arr); 
    29752981        Ngt3 = ret_arr[0]; 
    29762982        NorNdiv4= ret_arr[1]; 
     
    31603166        } 
    31613167        Foutfb = target_freq; 
    3162         int * ret_arr; 
    3163         ret_arr= calc_freq_vars(Fclk, try_freq); 
     3168        int ret_arr[6]; 
     3169        calc_freq_vars(Fclk, try_freq,ret_arr); 
    31643170        Ngt3_2 = ret_arr[0]; 
    31653171        NorNdiv4_2= ret_arr[1]; 
     
    32003206                synth_freq = Foutrx / 4; 
    32013207 
    3202         int * ret_arr; 
    3203         ret_arr= calc_phase_vars(Fclk, synth_freq,phsh); 
     3208        int  ret_arr[6]; 
     3209        calc_phase_vars(Fclk, synth_freq,phsh,ret_arr); 
    32043210        Qu_tx_Ngt3_3 = ret_arr[0]; 
    32053211        NorNdiv4_phsh_3= ret_arr[1]; 
     
    32383244                synth_freq = Fouttx / 4; 
    32393245 
    3240         int * ret_arr; 
    3241         ret_arr= calc_phase_vars(Fclk, synth_freq,phsh); 
     3246        int  ret_arr[6]; 
     3247        calc_phase_vars(Fclk, synth_freq,phsh,ret_arr); 
    32423248        Qu_tx_Ngt3_3 = ret_arr[0]; 
    32433249        NorNdiv4_phsh_3= ret_arr[1]; 
     
    32763282 
    32773283         
    3278         int * ret_arr; 
    3279         ret_arr= calc_phase_vars(Fclk, synth_freq,phsh); 
     3284        int  ret_arr[6]; 
     3285        calc_phase_vars(Fclk, synth_freq,phsh,ret_arr); 
    32803286        Qu_tx_Ngt3_3 = ret_arr[0]; 
    32813287        NorNdiv4_phsh_3= ret_arr[1];